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For the Inventor, By the Inventor

Hopewell Junction, NY, United States of America

Orazio Pasquale Forlenza

This inventor holds 19 USPTO granted patents and 1 published patent application, primarily in Built-In Self-Test Diagnostics. Top assignee: International Business Machines Corporation. Active years: 2001-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Orazio Pasquale Forlenza. Retrieved from https://idiyas.com/inventor/orazio-pasquale-forlenza

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 19 

% Patents Active = 68.4

Average Co-Inventor Count = 4.0

ph-index = 7

Forward Citations = 150(Granted Patents)


Location History:

  • Hopewell Junction, NC (US) (2016)
  • Hopewell Junction, NY (US) (2001 - 2022)

Company Filing History:

goldMedal19 out of 166,351 
 
International Business Machines Corporation
 patents

Years Active: 2001-2022

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Areas of Expertise:
Diagnostic Enhancement
Test Pattern Processor
Root Cause Identification
Scan Chain Defects
VLSI Diagnostics
Automated Testing
ABIST
Design-for-Test
Integrated Circuits
Diagnostic Methods
Fault Detection
Shift Registers
19 patents (USPTO):Explore Patents
1. 11378623 - Diagnostic enhancement for multiple instances of identical structures (2022-07-05),
2. 9274173 - Selective test pattern processor (2016-03-01),
3. 9274172 - Selective test pattern processor (2016-03-01),
4. 9244757 - Logic-built-in-self-test diagnostic method for root cause identification (2016-01-26),
5. 9244756 - Logic-built-in-self-test diagnostic method for root cause identification (2016-01-26),
6. 8086924 - Implementing diagnosis of transitional scan chain defects using logic built in self test LBIST test patterns (2011-12-27),
7. 8065575 - Implementing isolation of VLSI scan chain using ABIST test patterns (2011-11-22),
8. 7934134 - Method and apparatus for performing logic built-in self-testing of an integrated circuit (2011-04-26),
9. 7930601 - AC ABIST diagnostic method, apparatus and program product (2011-04-19),
10. 7921346 - Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD) (2011-04-05),
11. 7908532 - Automated system and processing for expedient diagnosis of broken shift registers latch chains (2011-03-15),
12. 7475308 - implementing deterministic based broken scan chain diagnostics (2009-01-06),
13. 7395470 - Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain (2008-07-01),
14. 7395469 - Method for implementing deterministic based broken scan chain diagnostics (2008-07-01),
15. 7392449 - Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain (2008-06-24),

Title: Orazio Pasquale Forlenza: Innovator in Semiconductor Testing

Introduction

Orazio Pasquale Forlenza is a prominent inventor based in Hopewell Junction, NY, known for his significant contributions to the field of semiconductor testing. With a remarkable portfolio consisting of 19 patents, Forlenza has established himself as a key player in innovation within the technology sector.

Latest Patents

Two of Forlenza's latest patents showcase his inventive prowess. The first, titled "Diagnostic enhancement for multiple instances of identical structures," outlines a method for executing tests on built-in self-test circuits. This method includes comparing results from two structures to identify faulty latches within stump chains.

The second patent, "Selective test pattern processor," describes a comprehensive approach for testing semiconductor devices. This invention allows users to select subsets from a series of test patterns and catalog them to generate test data applicable to the devices, enhancing efficiency in semiconductor testing processes.

Career Highlights

Forlenza has been affiliated with International Business Machines Corporation (IBM), where he has contributed to innovative designs and methodologies in semiconductor technology. His work has not only advanced testing protocols but has also optimized performance evaluation for integrated circuits.

Collaborations

Throughout his career, Forlenza has collaborated with esteemed colleagues, including Donato Orazio Forlenza and Phong T Tran. These partnerships have led to the development of cutting-edge technologies that significantly improve test processes, exemplifying the power of teamwork in innovation.

Conclusion

Orazio Pasquale Forlenza's contributions to semiconductor testing reflect his dedication to innovation and excellence. With his extensive portfolio of patents and collaborative work at IBM, he continues to make significant strides in enhancing the efficiency and accuracy of semiconductor device testing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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