The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2011
Filed:
Feb. 22, 2008
Joseph Eckelman, Hopewell Jct., NY (US);
Donato O. Forlenza, Hopewell Junction, NY (US);
Orazio P. Forlenza, Hopewell Junction, NY (US);
William J. Hurley, Walpole, MA (US);
Thomas J. Knips, Wappingers Falls, NY (US);
Gary William Maier, Poughquag, NY (US);
Phong T. Tran, Highland, NY (US);
Joseph Eckelman, Hopewell Jct., NY (US);
Donato O. Forlenza, Hopewell Junction, NY (US);
Orazio P. Forlenza, Hopewell Junction, NY (US);
William J. Hurley, Walpole, MA (US);
Thomas J. Knips, Wappingers Falls, NY (US);
Gary William Maier, Poughquag, NY (US);
Phong T. Tran, Highland, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.