The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2008

Filed:

Apr. 08, 2004
Applicants:

Adrian C. Anderson, Lagrangeville, NY (US);

Todd Michael Burdine, Wappingers Falls, NY (US);

Donato Orazio Forlenza, Hopewell Junction, NY (US);

Orazio Pasquale Forlenza, Hopewell Junction, NY (US);

William James Hurley, Poughkeepsie, NY (US);

Phong T. Tran, Poughkeepsie, NY (US);

Inventors:

Adrian C. Anderson, Lagrangeville, NY (US);

Todd Michael Burdine, Wappingers Falls, NY (US);

Donato Orazio Forlenza, Hopewell Junction, NY (US);

Orazio Pasquale Forlenza, Hopewell Junction, NY (US);

William James Hurley, Poughkeepsie, NY (US);

Phong T. Tran, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.


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