The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2011
Filed:
Jun. 05, 2008
Donato O. Forlenza, Hopewell Junction, NY (US);
Orazio P. Forlenza, Hopewell Junction, NY (US);
Bryan J. Robbins, Beavercreek, OH (US);
Phong T. Tran, Highland, NY (US);
Donato O. Forlenza, Hopewell Junction, NY (US);
Orazio P. Forlenza, Hopewell Junction, NY (US);
Bryan J. Robbins, Beavercreek, OH (US);
Phong T. Tran, Highland, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.