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For the Inventor, By the Inventor

Folsom, CA, United States of America

Navneet Dour

This inventor holds 17 USPTO granted patents and 1 published patent application, primarily in Memory Testing Technology. Top assignee: Intel Corporation. Active years: 2001-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Navneet Dour. Retrieved from https://idiyas.com/inventor/navneet-dour

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 17 

% Patents Active = 70.6

Average Co-Inventor Count = 2.6

ph-index = 6

Forward Citations = 214(Granted Patents)


Location History:

  • Fair Oaks, CA (US) (2001 - 2006)
  • Folsom, CA (US) (2006 - 2010)
  • El Dorado Hills, CA (US) (2020 - 2023)

Company Filing History:

goldMedal17 out of 56,365 
 
Intel Corporation
 patents

Years Active: 2001-2023

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Areas of Expertise:
Duty Cycle Correction
Delay-Locked Loop
Memory Test Traffic Router
Secured Hardware
Synchronized Clock
Wake-Up Circuit
Calibrating Receivers
On-Die Termination
PVT Controller
Driver Impedance Control
Power-Up Sequencing
AC Timings
17 patents (USPTO):Explore Patents
1. 11722128 - Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL) (2023-08-08),
2. 11070200 - Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL) (2021-07-20),
3. 11042315 - Dynamically programmable memory test traffic router (2021-06-22),
4. 10613955 - Platform debug and testing with secured hardware (2020-04-07),
5. 7751274 - Extended synchronized clock (2010-07-06),
6. 7746135 - Wake-up circuit (2010-06-29),
7. 7602859 - Calibrating integrating receivers for source synchronous protocol (2009-10-13),
8. 7432731 - Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations (2008-10-07),
9. 7403034 - PVT controller for programmable on die termination (2008-07-22),
10. 7307900 - Method and apparatus for optimizing strobe to clock relationship (2007-12-11),
11. 7020818 - Method and apparatus for PVT controller for programmable on die termination (2006-03-28),
12. 7012451 - Slew rate at buffers by isolating predriver from driver (2006-03-14),
13. 7009894 - Dynamically activated memory controller data termination (2006-03-07),
14. 6617891 - Slew rate at buffers by isolating predriver from driver (2003-09-09),
15. 6563337 - Driver impedance control mechanism (2003-05-13),

Title: Inventor Navneet Dour: Pioneering Innovations in Folsom, CA

Introduction: Navneet Dour is a visionary inventor based in Folsom, CA, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Navneet Dour holds several patents in the areas of artificial intelligence, renewable energy, and sustainable technologies, showcasing his commitment to creating a more sustainable future.

Career Highlights: With a background in engineering and a passion for problem-solving, Navneet Dour has led numerous successful projects that have revolutionized industries and improved the lives of many.

Collaborations: Throughout his career, Navneet Dour has collaborated with leading tech companies, research institutions, and universities to bring his innovative ideas to life and make a lasting impact on society.

Conclusion: Navneet Dour's dedication to innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors and shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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