The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Mar. 29, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Lakshminarayana Pappu, Folsom, CA (US);

Christopher E. Cox, Placerville, CA (US);

Navneet Dour, El Dorado Hills, CA (US);

Asaf Rubinstein, Tel-Aviv, IL;

Israel Diamand, Aderet, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0888 (2016.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0635 (2013.01); G06F 3/0616 (2013.01); G06F 3/0685 (2013.01); G06F 12/0888 (2013.01); G06F 13/1668 (2013.01); G06F 13/4282 (2013.01); G06F 2212/60 (2013.01); G06F 2213/0026 (2013.01);
Abstract

In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.


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