The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2009

Filed:

Apr. 28, 2005
Applicants:

Roger K. Cheng, San Jose, CA (US);

Harishankar Sridharan, Folsom, CA (US);

Navneet Dour, Folsom, CA (US);

Hing Y. to, Cupertino, CA (US);

Inventors:

Roger K. Cheng, San Jose, CA (US);

Harishankar Sridharan, Folsom, CA (US);

Navneet Dour, Folsom, CA (US);

Hing Y. To, Cupertino, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 27/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An embodiment of the present invention is a technique to calibrate an integrating receiver. A delay calibration circuit calibrates an adjusting code of a chain of delay elements and positioning of at least an integrating strobe used to define an integration window for the integrating receiver. An integrating receiver pulse generator generates an IR pulse from the at least integrating strobe. A calibration controller controls calibrating the adjusting code and the positioning of the at least integrating strobe.


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