Intel Corporation

Navneet Dour

Roger K Cheng

Christopher E Cox

Adhiveeraraghavan Srikanth

Bryan K Casper

Aaron K Martin

George Vergis

Lakshminarayana Pappu

Ganesh Balamurugan

Frank Patrick O'Mahony

Mozhgan Mansuri

Joe Salmon

Harishankar Sridharan

Ajay Balankutty

Kuan Zhou

Sridhar Tirumalai

Krishnamurthy Venkataramana

Alex Thomas

Hari Venkatramani

Quoc Nguyen

Kuljit Singh Bains

Zohar Bogin

Hing Yan To

Joseph H Salmon

Anoop Mukker

Israel Diamand

Asaf Rubinstein

Hany M Fahmy

Jacob Schneider

Dave Freker

An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)

In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

Dynamically programmable memory test traffic router

A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable testing of the connections to the memory devices. The test control circuitry is triggered separately from the other power control circuitry, and can be protected to allow only secured access for testing.

Platform debug and testing with secured hardware

Some embodiments are directed to circuits comprising first and second PLLs. The first PLL generates a first clock signal based on a reference clock signal. The second PLL generates a second clock signal based on the reference clock signal and is synchronized with the first clock signal.

Extended synchronized clock

Disclosed herein is a wake-up circuit for a bias input of a circuit such as a slave DLL circuit, to allow it to be placed in a reduced power mode and be 'awoken' (brought up to a control bias level) in a sufficiently small enough amount of time. The wake-up circuit couples a bias input node to a voltage level that is higher then the control bias level in response to a wake-up event, and then it couples the control bias node to the bias input node in response to their voltage levels being sufficiently close to one another.

Wake-up circuit

An embodiment of the present invention is a technique to calibrate an integrating receiver. A delay calibration circuit calibrates an adjusting code of a chain of delay elements and positioning of at least an integrating strobe used to define an integration window for the integrating receiver. An integrating receiver pulse generator generates an IR pulse from the at least integrating strobe. A calibration controller controls calibrating the adjusting code and the positioning of the at least integrating strobe.

Calibrating integrating receivers for source synchronous protocol

An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.

Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations

Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die termination circuit allows for faster transfer rates over communication lines by reducing the time needed to recover from signal reflection and similar issues.

PVT controller for programmable on die termination

To allow a memory controller to synchronize strobe to clock relationship for a DRAM, a register, such as, a flip flop, is incorporated within the DRAM to facilitate the sampling of SCLK with DQS. Likewise, while the DRAM is in a test mode of operation, the memory controller advances or retards the clock to DQS at the memory controller hub (MCH) to achieve the proper DRAM relationship. In one embodiment, the memory controller advances DQS if a binary zero value is read. In contrast, the memory controller retards DQS if a binary one value is read.

Method and apparatus for optimizing strobe to clock relationship

Method and apparatus for PVT controller for programmable on die termination

In one embodiment, a pre-driver generates pre-driving signals based on control signals provided by a control circuit. The pre-driver has pre-driver power and ground connections. The pre-driving signals operate at a frequency band. A driver generates an output signal based on the pre-driving signals at an output pad. The output signal has a slew rate. The driver has driver power and ground connections. A low pass filter is coupled between the pre-driver and the driver power and ground connections to reduce the effect of noise at the pre-driving signals. The low pass filter has a cut-off frequency corresponding to the frequency of noise. In another embodiment, a plurality of pre-drivers generates pre-driving signals based on control signals provided by a control circuit. The pre-drivers have pre-driver power and ground connections. A plurality of drivers generates a plurality of output signals based on the pre-driving signals at output pads of an integrated circuit. Each of the output signals has a slew rate. The drivers have driver power and ground connections. On-die pre-driver power and ground planes are coupled to the pre-driver power and ground connections on die of the integrated circuit, respectively. On-die driver power and ground planes are coupled to the driver power and ground connections on-die of the integrated circuit, respectively. The driver power and ground planes are separated from the pre-driver power and ground planes on the die, and/or on the package to maintain the desired slew rate.

Slew rate at buffers by isolating predriver from driver

A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memory, deactivating the termination loads. The method also involves, for a second read of information from the memory, activating the termination loads.

Dynamically activated memory controller data termination

In one embodiment, a driver impedance control mechanism is adapted for a circuit board. The driver impedance control mechanism comprises (i) an integrated circuit including at least one driver circuit operating as a pull-up driver and a pull-down driver, (ii) a link coupled to an interface pin of the integrated circuit, the interface pin receiving signals from the at least one driver circuit, and (iii) a single resistive element terminating the link and separately compensating the at least one driver when operating as the pull-up driver and the pull-down driver and supplying the same impedance control bits to all driver to have good signal quality over the interface.

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Folsom, CA, United States of America

Navneet Dour