The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Jun. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aaron Martin, El Dorado Hills, CA (US);

Roger Cheng, San Jose, CA (US);

Hari Venkatramani, San Jose, CA (US);

Navneet Dour, El Dorado Hills, CA (US);

Mozhgan Mansuri, Hillsboro, OR (US);

Bryan Casper, Ridgefield, WA (US);

Frank O'Mahony, Portland, OR (US);

Ganesh Balamurugan, Hillsboro, OR (US);

Ajay Balankutty, Hillsboro, OR (US);

Kuan Zhou, Portland, OR (US);

Sridhar Tirumalai, Chandler, AZ (US);

Krishnamurthy Venkataramana, Folsom, CA (US);

Alex Thomas, El Dorado Hills, CA (US);

Quoc Nguyen, El Dorado Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/156 (2006.01); H03L 7/081 (2006.01); G11C 7/22 (2006.01); G06F 1/08 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1565 (2013.01); G06F 1/08 (2013.01); G11C 7/1057 (2013.01); G11C 7/1066 (2013.01); G11C 7/1084 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); H03L 7/0812 (2013.01);
Abstract

An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.


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