Dublin, CA, United States of America

Narasimha R Lanka

This inventor holds 25 USPTO granted patents and 11 published patent applications and 4 EPO patents, primarily in Die-to-Die Interconnects. Top assignees: Intel Corporation, Intel Products IP LLC. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Narasimha R Lanka. Retrieved from https://idiyas.com/inventor/narasimha-r-lanka

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 25 

% Patents Active = 96.0

 

Average Co-Inventor Count = 5.3

ph-index = 2

Forward Citations = 21(Granted Patents)


Location History:

  • San Jose, CA (US) (2017 - 2020)
  • Dublin, CA (US) (2020 - 2024)

Company Filing History:


Years Active: 2017-2026

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Areas of Expertise:
Die-to-Die Adapter
Clock Phase Management
Lane Repair
Lane Reversal
Link Layer-PHY Interface
On-Package Interconnect
Universal Chiplet Interconnect Express
Retimers
Signal Validation
Latency Sensitivity
Compliance Testing
Multi-Chip Package
25 patents (USPTO):Explore Patents

Title: The Innovative Contributions of Narasimha Lanka

Introduction

Narasimha Lanka is a prominent inventor based in Dublin, California. He has made significant contributions to the field of technology, particularly in the area of die-to-die interconnects. With a total of five patents to his name, his work has had a substantial impact on the industry.

Latest Patents

One of Narasimha's latest patents is titled "Link initialization training and bring up for die-to-die interconnect." This invention involves an apparatus that includes a die-to-die adapter designed to communicate with both a protocol layer and physical layer circuitry. The physical layer circuitry is responsible for receiving and outputting information to a second die via an interconnect. After a reset flow for the first die, the circuitry performs a sideband initialization to detect the completion of a reset flow for the second die. Following this, it conducts a mainband initialization at the lowest speed, eventually progressing to a mainband training at a negotiated data rate.

Another notable patent is "Clock-gating in die-to-die (D2D) interconnects." This invention addresses actions to be taken on various lanes of a D2D interconnect during a clock-gating event. The physical layer logic directs the PHY electrical circuitry to set the state of the lanes based on whether the D2D interconnect is terminated or unterminated.

Career Highlights

Narasimha Lanka is currently employed at Intel Corporation, where he continues to innovate and develop new technologies. His work at Intel has positioned him as a key player in advancing interconnect technology.

Collaborations

Throughout his career, Narasimha has collaborated with notable colleagues, including Swadesh Choudhary and Debendra Das Sharma. These collaborations have further enriched his contributions to the field.

Conclusion

Narasimha Lanka's innovative patents and contributions to die-to-die interconnect technology highlight his expertise and dedication to advancing the industry. His work at Intel Corporation and collaborations with esteemed colleagues underscore his significant role in technological innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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