The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2025
Filed:
Apr. 29, 2022
Intel Corporation, Santa Clara, CA (US);
Narasimha Lanka, Dublin, CA (US);
Debendra Das Sharma, Saratoga, CA (US);
Lakshmipriya Seshan, Sunnyvale, CA (US);
Gerald Pasdast, San Jose, CA (US);
Zuoguo Wu, San Jose, CA (US);
Swadesh Choudhary, Mountain View, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.