The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Jun. 20, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Lakshmipriya Seshan, Sunnyvale, CA (US);

Gerald Pasdast, San Jose, CA (US);

Peipei Wang, San Jose, CA (US);

Narasimha Lanka, Dublin, CA (US);

Swadesh Choudhary, Mountain View, CA (US);

Zuoguo Wu, San Jose, CA (US);

Debendra Das Sharma, Saratoga, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/347 (2020.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/347 (2020.01); G06F 30/392 (2020.01);
Abstract

In one embodiment, an apparatus includes a first die comprising: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry, where the die-to-die adapter is to receive first information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter. The physical layer circuitry is configured to receive and output the first information to a second die via an interconnect and comprises: a first plurality of transmitters to transmit data via a first plurality of data lanes; and at least one redundant transmitter. The physical layer circuitry may be configured to remap a first data lane of the first plurality of data lanes to the at least one redundant transmitter. Other embodiments are described and claimed.


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