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For the Inventor, By the Inventor

Brookline, MA, United States of America

Matthew T Currie

This inventor holds 98 USPTO granted patents and 7 EPO patents, primarily in Semiconductor Structures (CPC class H01L29-7842). Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Amberwave Systems Corporation. Active years: 2003-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Matthew T Currie. Retrieved from https://idiyas.com/inventor/matthew-t-currie

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 98

% Patents Active = 88.8

 

Average Co-Inventor Count = 2.8

ph-index = 22

Forward Citations = 2,705(Granted Patents)

Forward Citations (Not Self Cited) = 2,491(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Boston, MA (US) (2003 - 2009)
  • Windham, NH (US) (2004 - 2012)
  • Brookline, MA (US) (2006 - 2020)

Company Filing History:

goldMedal52 out of 42,926 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal46 out of 85 
 
Amberwave Systems Corporation
 patents

Years Active: 2003-2020

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Areas of Expertise:
Strained Semiconductor
Heterostructures
Dynamic Random Access Memory
Gate Electrodes
Transistor Structures
Dislocation Defects
Material Layers
Device Fabrication
Silicon Germanium
Impurity Gradients
Field-Effect Transistor
Semiconductor Devices
98 patents (USPTO):Explore Patents
1. 10629735 - Reacted conductive gate electrodes and methods of making the same (2020-04-21),
2. 10510581 - Methods of forming strained-semiconductor-on-insulator device structures (2019-12-17),
3. 10164015 - Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same (2018-12-25),
4. 10050145 - Methods for forming semiconductor device structures (2018-08-14),
5. 9934964 - Semiconductor heterostructures having reduced dislocation pile-ups and related methods (2018-04-03),
6. 9923057 - Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same (2018-03-20),
7. 9812572 - Reacted conductive gate electrodes and methods of making the same (2017-11-07),
8. 9601623 - Methods for forming semiconductor device structures (2017-03-21),
9. 9548236 - Methods of forming strained-semiconductor-on-insulator device structures (2017-01-17),
10. 9508724 - Strained channel dynamic random access memory devices (2016-11-29),
11. 9431243 - Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication (2016-08-30),
12. 9343539 - Reacted conductive gate electrodes and methods of making the same (2016-05-17),
13. 9309607 - Semiconductor heterostructures having reduced dislocation pile-ups and related methods (2016-04-12),
14. 9293582 - Hybrid fin field-effect transistor structures and related methods (2016-03-22),
15. 9281376 - Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same (2016-03-08),

Title: The Innovative Journey of Matthew T Currie

Introduction: Matthew T Currie, a talented inventor hailing from Brookline, MA (US), has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Matthew T Currie's latest patents showcase his ingenuity and forward-thinking approach to problem-solving in various industries.

Career Highlights: Throughout his illustrious career, Matthew T Currie has been recognized for his exceptional creativity and ability to transform ideas into tangible inventions that have the potential to shape the future.

Collaborations: Matthew T Currie has collaborated with leading companies, research institutions, and universities to further develop his inventions and bring them to market, solidifying his reputation as a visionary inventor.

Conclusion: Matthew T Currie's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors, leaving an indelible mark on the world of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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