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Salem, NH, United States of America

Amberwave Systems Corporation

USPTO Granted Patents = 85

% Expired Patents = 1.2

Forward Citations = 3,557

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19 inventors (with patents filed for the assignee):

Matthew T Currie (46 out of 98 patents)

Eugene A Fitzgerald (40 out of 120 patents)

Anthony J Lochtefeld (35 out of 114 patents)

4. Richard Hammond (17 out of 60 patents)

5. Thomas A Langdo (14 out of 42 patents)

6. Mayank T Bulsara (9 out of 16 patents)

7. Christopher W Leitz (8 out of 25 patents)

8. Richard Charles Westhoff (7 out of 21 patents)

9. Eugene A Fitzergald (7 out of 7 patents)

10. Christopher J Vineis (6 out of 18 patents)

11. Glyn Braithwaite (4 out of 16 patents)

12. Vicky K Yang (4 out of 9 patents)

13. Nicole Gerrish (2 out of 3 patents)

14. Curtis D Gridley (2 out of 3 patents)

15. Dimitri A Antoniadis (2 out of 12 patents)

Core Competencies:

Strained-Semiconductor-On-Insulator

CMOS Processing

Dynamic Random Access Memory

Heterostructures

Silicon Germanium

Transistor Structures

Epitaxial Growth

Gate Technology

Dislocation Management

Integrated Circuits

High Speed Electronics

Optoelectronic Material

85 patents: Sort by Forward Citations

1. 7638842 - Lattice-mismatched semiconductor structures on insulators (2009-12-29),

2. 7626246 - Solutions for integrated circuit integration of alternative active area materials (2009-12-01),

3. 7615829 - Elevated source and drain elements for strained-channel heterojuntion field-effect transistors (2009-11-10),

4. 7594967 - Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy (2009-09-29),

5. 7588994 - Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain (2009-09-15),

6. 7566606 - Methods of fabricating semiconductor devices having strained dual channel layers (2009-07-28),

7. 7541208 - Methods for preserving strained semiconductor substrate layers during CMOS processing (2009-06-02),

8. 7504704 - Shallow trench isolation process (2009-03-17),

9. 7501351 - Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits (2009-03-10),

10. 7494881 - Methods for selective placement of dislocation arrays (2009-02-24),

11. 7465619 - Methods of fabricating dual layer semiconductor devices (2008-12-16),

12. 7439164 - Methods of fabricating semiconductor structures having epitaxially grown source and drain elements (2008-10-21),

13. 7432139 - Methods for forming dielectrics and metal electrodes (2008-10-07),

14. 7420201 - Strained-semiconductor-on-insulator device structures with elevated source/drain regions (2008-09-02),

15. 7416909 - Methods for preserving strained semiconductor substrate layers during CMOS processing (2008-08-26),

Company Overview

Amberwave Systems Corporation, based in Salem, NH, specializes in advanced strained semiconductor technology, focusing on enhancing the performance of electronic devices. The company develops innovative solutions in areas such as Strained-Semiconductor-On-Insulator, CMOS processing, and dynamic random access memory. Their expertise extends to heterostructures, silicon germanium, and advanced transistor structures, leveraging epitaxial growth and gate technology to push the boundaries of semiconductor applications in various industries.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

85 Patents

#2 in Salem, NH

#30 in New Hampshire

#4,378 in US

#8,962 in the World

Salem, NH, United States of America

Amberwave Systems Corporation

Forward Citations = 3,557

19 inventors:

Matthew T Currie (46 out of 98 patents)

Eugene A Fitzgerald (40 out of 120 patents)

Anthony J Lochtefeld (35 out of 114 patents)

4. Richard Hammond (17 out of 60 patents)

5. Thomas A Langdo (14 out of 42 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Amberwave Systems Corporation. Retrieved from https://idiyas.com/company/amberwave-systems

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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