Kawasaki, Japan

Masahito Kanamura

This inventor holds 22 USPTO granted patents and 8 published patent applications and 1 EPO patent, primarily in Semiconductor Devices. Top assignees: Fujitsu Corporation, Sumitomo Electric Device Innovations, Inc., Transphorm Inc.. Active years: 2010-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Masahito Kanamura. Retrieved from https://idiyas.com/inventor/masahito-kanamura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 22 

% Patents Active = 72.7

 

Average Co-Inventor Count = 1.9

ph-index = 5

Forward Citations = 73(Granted Patents)


Location History:

  • Kawasaki, JP (2010 - 2017)
  • Fukusima, JP (2017)
  • Isehara, JP (2014 - 2018)

Company Filing History:


Years Active: 2010-2018

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Areas of Expertise:
Semiconductor Device
Manufacturing Method
Compound Semiconductor
III-N Device
Multi-Layer Structure
Ohmic Contacts
Film Structure
Electrode Design
Device Fabrication
Work Functions
Layered Structures
22 patents (USPTO):Explore Patents

Title: Masahito Kanamura: Innovator in Semiconductor Technology

Introduction: Masahito Kanamura is a notable inventor based in Kawasaki, Japan, recognized for his contributions to semiconductor technology. With an impressive portfolio of 22 patents, Kanamura has played a significant role in advancing the development and manufacturing processes of semiconductor devices.

Latest Patents: Kanamura's latest innovations include two important patents related to semiconductor devices. The first patent describes a semiconductor device that features three semiconductor layers made of nitride semiconductor stacked on a substrate. This device includes a drain electrode on the third semiconductor layer, a gate electrode on the same layer, and a source electrode that penetrates the second and third layers, revealing the first semiconductor layer. The source electrode comprises a first conductor layer in contact with the first layer and a second conductor layer that is in contact with the second layer, with a notable difference in work function materials used for each layer.

The second patent focuses on another semiconductor device configuration that includes a first semiconductor layer above a substrate and a second layer on top. It encompasses a source electrode and a drain electrode over the second layer, an insulating film, a gate electrode, and a protective film formed via thermal CVD, thermal ALD, or vacuum vapor deposition methods.

Career Highlights: Masahito Kanamura has held significant positions within leading companies in the technology sector. He has worked at Fujitsu Corporation, where he contributed to various semiconductor projects. He also spent time at Transphorm Inc., further expanding his knowledge and experience in the field of semiconductor devices manufacturing.

Collaborations: Throughout his career, Kanamura has collaborated with several industry experts, including his coworkers Toshihide Kikkawa and Toshihiro Ohki. These collaborations have played a crucial role in refining his inventions and enhancing the technological advancements within his projects.

Conclusion: Masahito Kanamura stands out as an innovative figure in semiconductor technology. His extensive patent portfolio signifies his dedication to improving device manufacturing processes and his impact on the industry. His work continues to influence the field and inspires future innovations in semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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