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For the Inventor, By the Inventor

San Jose, CA, United States of America

Mark W Randolph

This inventor holds 87 USPTO granted patents and 1 published patent application and 2 EPO patents, primarily in Flash Memory Technology (CPC class G11C1-604). Top assignees: Advanced Micro Devices Corporation, Spansion LLC., Cypress Semiconductor Corporation. Active years: 1999-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mark W Randolph. Retrieved from https://idiyas.com/inventor/mark-w-randolph

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 87 

% Patents Active = 79.3


Average Co-Inventor Count = 3.8

ph-index = 19

Forward Citations = 1,211(Granted Patents)

Forward Citations (Not Self Cited) = 1,168(Dec 10, 2025)


Inventors with similar research interests:

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Company Filing History:

goldMedal48 out of 13,200 
 
Advanced Micro Devices Corporation
 patents
silverMedal37 out of 1,075 
 
Spansion LLC.
 patents
bronzeMedal2 out of 3,600 
 
Cypress Semiconductor Corporation
 patents
4. 1 out of 24 
 
Advance Micro Devices, Inc.
 patents
5. 1 out of 6 
 
Fujitsu Amd Semiconductor Limited
 patents
6. 1 out of 39,387 
 
Fujitsu Corporation
 patents
7. 1 out of 834,708 
Other
 patents
where one patent can have more than one assignee

Years Active: 1999-2016

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Areas of Expertise:
Charge Protection
Leakage Reduction
Flash Memory
Memory Cell
Programming
Non-Volatile Memory
Soft Programming
Threshold Voltage
High K Dielectric
Wordline Protection
Data Retention
Silicon-Rich Nitride
87 patents (USPTO):Explore Patents
1. 9318373 - Method and apparatus for protection against process-induced charging (2016-04-19),
2. 9196624 - Leakage reducing writeline charge protection circuit (2015-11-24),
3. 8995198 - Multi-pass soft programming (2015-03-31),
4. 8957472 - Memory device having trapezoidal bitlines and method of fabricating same (2015-02-17),
5. 8938655 - Extending flash memory data retension via rewrite refresh (2015-01-20),
6. 8803216 - Memory cell system using silicon-rich nitride (2014-08-12),
7. 8445966 - Method and apparatus for protection against process-induced charging (2013-05-21),
8. 8404541 - Strapping contact for charge protection (2013-03-26),
9. 8203178 - System and method for reducing process-induced charging (2012-06-19),
10. 8125018 - Memory device having trapezoidal bitlines and method of fabricating same (2012-02-28),
11. 8031528 - Flash memory programming and verification with reduced leakage current (2011-10-04),
12. 7995386 - Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb (2011-08-09),
13. 7944746 - Room temperature drift suppression via soft program after erase (2011-05-17),
14. 7855114 - High K stack for non-volatile memory (2010-12-21),
15. 7804125 - System and method for reducing process-induced charging (2010-09-28),

Title: Mark W Randolph - Innovator from San Jose, CA

Introduction: Mark W Randolph is a renowned inventor based in San Jose, California, known for his groundbreaking contributions to various industries.

Latest Patents: Mark W Randolph holds several patents in the fields of technology, healthcare, and consumer electronics, showcasing his diverse range of innovative ideas.

Career Highlights: With a career spanning over two decades, Mark has worked with top companies in Silicon Valley, leading research and development teams to create cutting-edge solutions.

Collaborations: Throughout his career, Mark has collaborated with leading universities and research institutions to further his inventions, demonstrating his commitment to pushing the boundaries of innovation.

Conclusion: Mark W Randolph's passion for innovation and his relentless drive to create have solidified his reputation as a pioneering inventor in the vibrant tech hub of San Jose, California.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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