Advanced Micro Devices Corporation

Spansion Llc.

Cypress Semiconductor Corporation

Other

Fujitsu Corporation

Advance Micro Devices, Inc.

Fujitsu Amd Semiconductor Limited

Mark W Randolph

Yi He

Zhizheng Liu

Wei Zheng

Mark T Ramsbey

Sameer S Haddad

Darlene G Hamilton

Ashot Melik-Martirosian

Edward Franklin Runnion

Hidehiko Shiraiwa

Timothy J Thurgate

Meng Ding

Richard M Fastow

Chi K Chang

Yu Nan Sun

Nicholas H Tripsas

Scott D Luning

Shane Charles Hollmer

Tazrien Kamal

Edward Hsia

Gulzar Ahmed Kathawala

Zengtao Liu

Angela Tai Hui

Zoran Krivokapic

Hiroyuki Kinoshita

Pau-Ling Chen

Daniel Sobek

Ming Sang Kwan

Sung-Yong Chung

David Michael Rogers

Kulachet Tanpairoj

Janet S Wang

Michael David Fliesler

Jack F Thomas

Mimi Xuefeng Qian

Gwyn Robert Jones

Ashot Melik Martirosian

Fei Wang

Arvind Halliyal

Mark S Chang

Binh Quang Le

Unsoon Kim

Jean Y Yang

Vei-Han Chan

Ming-Huei Shieh

Hung-Sheng Chen

Tatsuya Kajita

Satoshi Torii

Harpreet Kaur Sachar

Emmanuil Lingunis

Michael A VanBuskirk

Nga-Ching Wong

Sung-Chul Lee

Pauling Chen

Roni Kornitz

Eric M Ajimine

Kwadwo A Appiah

Ed Runnion

Tuan Duc Pham

Kuo-Tung Chang

Cyrus E Tabery

Lee Edward Cleveland

Simon S Chan

Yue-Song He

Narbeh Derhacobian

Ravi S Sunkavalli

Joong Jeon

Lei Xue

Shankar Sinha

Amol Ramesh Joshi

Jean Yee-Mei Yang

Jaeyong Park

Xuguang Alan Wang

Scott Luning

Shivananda Shetty

Jeff P Erhardt

Weidong Qian

Masaaki Higashitani

Michael Van Buskirk

Harry Kuo

Ming-Sang Kwan

Michael Brennan

Fred T K Cheung

Sean Michael O'Mullan

Boon-Yong Ang

Mimi Lee

Alykhan Madhani

Tio Wei Neo

Bradley Marc Davis

Robert Bertram Ogle, Jr

Ihsan Djomehri

Wei Zhang

Ian Morgan

John Anthony Darilek

Cindy Sun

Don Carlos Darling

Ken Tanpairoj

Adam Shackleton

Abhijit Raghunathan

Asif Arfi

A semiconductor device () for improved charge dissipation protection includes a substrate (), a layer of semiconductive or conductive material (), one or more thin film devices () and a charge passage device (). The thin film devices () are connected to the semiconductive or conductive layer () and the charge passage device () is coupled to the thin film devices () and to the substrate () and provides a connection from the thin film devices () to the substrate () to dissipate charge from the semiconductive/conductive layer () to the substrate ().

Method and apparatus for protection against process-induced charging

Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.

Leakage reducing writeline charge protection circuit

Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification.

Multi-pass soft programming

A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.

Memory device having trapezoidal bitlines and method of fabricating same

Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate.

Extending flash memory data retension via rewrite refresh

A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.

Memory cell system using silicon-rich nitride

A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Strapping contact for charge protection

A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.

System and method for reducing process-induced charging

A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Flash memory programming and verification with reduced leakage current

Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb

Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift.

Room temperature drift suppression via soft program after erase

A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.

High K stack for non-volatile memory

Growing community of inventors

San Jose, CA, United States of America

Mark W Randolph