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For the Inventor, By the Inventor

Hopewell Junction, NY, United States of America

Tomoko Ogura

This inventor holds 50 USPTO granted patents and 3 published patent applications and 1 EPO patent, primarily in Non-Volatile Memory (CPC class G11C). Top assignees: Halo Lsi, Inc., Halo Lsi Design Device Technology, Inc., Halo Lsi Device & Design Technology, Inc.. Active years: 1999-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tomoko Ogura. Retrieved from https://idiyas.com/inventor/tomoko-ogura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 50 

% Patents Active = 94.0


Average Co-Inventor Count = 2.7

ph-index = 14

Forward Citations = 741(Granted Patents)

Forward Citations (Not Self Cited) = 695(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Wappingers Falls, NY (US) (1999 - 2006)
  • Hopewell Jct, NY (US) (2002 - 2006)
  • Hopewell Jct., NY (US) (2003 - 2006)
  • Fishkill, NY (US) (2003 - 2006)
  • Hopewell Junction, NY (US) (2006)
  • Hillsboro, OR (US) (2007 - 2015)

Company Filing History:

goldMedal37 out of 57 
 
Halo Lsi, Inc.
 patents
silverMedal6 out of 11 
 
Halo Lsi Design Device Technology, Inc.
 patents
bronzeMedal2 out of 3 
 
Halo Lsi Device & Design Technology, Inc.
 patents
4. 2 out of 3 
 
New Halo, Inc.
 patents
5. 1 out of 1 
 
Gumbo Logic, Inc.
 patent
6. 1 out of 3 
 
Halo Lsi Design and Device Technologies, Inc.
 patents
7. 1 out of 3 
 
Halo, Inc.
 patents
8. 1 out of 27,375 
 
Matsushita Electric Industrial Co., Ltd.
 patents
where one patent can have more than one assignee

Years Active: 1999-2015

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Areas of Expertise:
Non-Volatile Memory
Twin MONOS Array
Trap-Charge Switch
High Speed Operation
Memory Array Organization
Ballistic Flash Memory
Charge Pump Circuit
Bit Line Decoding
Control Gate Decoder
Programmable Logic
Reference Method
50 patents (USPTO):Explore Patents
1. 9123419 - Complementary reference method for high reliability trap-type non-volatile memory (2015-09-01),
2. 8633544 - Twin MONOS array for high speed application (2014-01-21),
3. 8325542 - Complementary reference method for high reliability trap-type non-volatile memory (2012-12-04),
4. 8174885 - High speed operation method for twin MONOS metal bit array (2012-05-08),
5. 8139410 - Trap-charge non-volatile switch connector for programmable logic (2012-03-20),
6. 8089809 - Trap-charge non-volatile switch connector for programmable logic (2012-01-03),
7. 8027198 - Trap-charge non-volatile switch connector for programmable logic (2011-09-27),
8. 8023326 - Trap-charge non-volatile switch connector for programmable logic (2011-09-20),
9. 7936604 - High speed operation method for twin MONOS metal bit array (2011-05-03),
10. 7742336 - Trap-charge non-volatile switch connector for programmable logic (2010-06-22),
11. 7447077 - Referencing scheme for trap memory (2008-11-04),
12. 7352033 - Twin MONOS array for high speed application (2008-04-01),
13. 7190603 - Nonvolatile memory array organization and usage (2007-03-13),
14. 7149126 - Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory (2006-12-12),
15. 7118961 - Stitch and select implementation in twin MONOS array (2006-10-10),

Title: The Inventor Spotlight: Tomoko Ogura

Introduction:

Tomoko Ogura, a prolific inventor based in Hopewell Junction, NY, has left a remarkable legacy in the field of memory technology. With an impressive portfolio of 50 patents, Ogura's innovative contributions have significantly impacted the world of non-volatile memory devices.

Latest Patents:

Among his latest patents is the "Complementary reference method for high reliability trap-type non-volatile memory," which introduces methods for complementary pairing of memory cells. This innovative approach involves utilizing physical memory cells in complementary pairs and leveraging complementary pairs of reference cells for each erase block. Additionally, Ogura's "Twin MONOS array for high-speed application" patent revolutionizes memory array operations by introducing a novel stitch area configuration for word gates and control gates.

Career Highlights:

Ogura's career has been marked by his tenure at companies like Halo LSI, Inc. and Halo LSI Design & Device Technology, Inc. During his time at these renowned organizations, Ogura demonstrated his expertise in memory technology and made significant advancements in the field.

Collaborations:

Throughout his career, Ogura has collaborated with esteemed colleagues such as Seiki Ogura and Nori Ogura. Their collective efforts have led to groundbreaking innovations in memory device design and operation.

Conclusion:

In conclusion, Tomoko Ogura stands as a distinguished figure in the world of memory technology, with a wealth of patents and a history of successful collaborations. His contributions have not only advanced the field but have also paved the way for future innovations in non-volatile memory devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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