The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2014
Filed:
Mar. 31, 2008
Kimihiro Satoh, Portland, OR (US);
Tomoko Ogura, Hillsboro, OR (US);
Ki-tae Park, Hwasung, KR;
Nori Ogura, Hillsboro, OR (US);
Yoshitaka Baba, Beaverton, OR (US);
Kimihiro Satoh, Portland, OR (US);
Tomoko Ogura, Hillsboro, OR (US);
Ki-Tae Park, Hwasung, KR;
Nori Ogura, Hillsboro, OR (US);
Yoshitaka Baba, Beaverton, OR (US);
Halo LSI, Inc., Hillsboro, OR (US);
Abstract
A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.