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For the Inventor, By the Inventor

Hsinchu, Taiwan

Kuang-Wen Liu

This inventor holds 23 USPTO granted patents and 11 published patent applications, primarily in Memory Device Fabrication. Top assignees: Macronix International Co., Ltd., Macronix International, Col, Ltd., Macronix Internationalco., Ltd.. Active years: 2002-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kuang-Wen Liu. Retrieved from https://idiyas.com/inventor/kuang-wen-liu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 23 

% Patents Active = 91.3

Average Co-Inventor Count = 2.5

ph-index = 4

Forward Citations = 35(Granted Patents)


Location History:

  • Nan-Tao Hsien, TW (2002)
  • Nantou County, TW (2003)
  • Nantou, TW (2004 - 2011)
  • Hsinchu County, TW (2014 - 2021)
  • Hsinchu, TW (2003 - 2022)
  • Hsin-chu, TW (2024)

Company Filing History:

goldMedal21 out of 3,609 
 
Macronix International Co., Ltd.
 patents
silverMedal1 out of 1 
 
Macronix International, Col, Ltd.
 patent
bronzeMedal1 out of 12 
 
Macronix Internationalco., Ltd.
 patents

Years Active: 2002-2024

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Areas of Expertise:
Memory Device
Semiconductor Structure
Fabrication Method
SONOS Device
3D Memory Device
Photo Pattern Method
Via Etching Rate
Threshold Voltage
Multi-Layer Circuits
Salicide Solution
23 patents (USPTO):Explore Patents
1. 11991882 - Method for fabricating memory device (2024-05-21),
2. 11917828 - Memory devices with multiple string select line cuts (2024-02-27),
3. 11374099 - 3D memory device including source line structure comprising composite material (2022-06-28),
4. 11211401 - Memory device and method for fabricating the same (2021-12-28),
5. 11183513 - Semiconductor device and method for fabricating the same (2021-11-23),
6. 10867909 - Semiconductor structure and method of fabricating wiring structure (2020-12-15),
7. 9741607 - Photo pattern method to increase via etching rate (2017-08-22),
8. 9583495 - Method for fabricating memory device (2017-02-28),
9. 9536808 - Photo pattern method to increase via etching rate (2017-01-03),
10. 9530786 - Memory device and method for fabricating the same (2016-12-27),
11. 9384989 - Sonos device and method for fabricating the same (2016-07-05),
12. 9245901 - Memory device and method for fabricating the same (2016-01-26),
13. 9153535 - Line layout and method of spacer self-aligned quadruple patterning for the same (2015-10-06),
14. 8803223 - SONOS device and method for fabricating the same (2014-08-12),
15. 7923770 - Memory device and method of fabricating the same (2011-04-12),

Title: The Innovative Journey of Inventor Kuang-Wen Liu

Introduction: Kuang-Wen Liu, a talented inventor hailing from Hsinchu, Taiwan, has made significant contributions to the field of technology through his groundbreaking innovations and patents.

Latest Patents: Kuang-Wen Liu's latest patents focus on advancements in semiconductor technology, particularly in the development of cutting-edge microchips with enhanced performance and efficiency.

Career Highlights: With a career spanning over two decades, Kuang-Wen Liu has established himself as a leading figure in the tech industry. His work has been instrumental in shaping the future of semiconductor manufacturing and design.

Collaborations: Throughout his career, Kuang-Wen Liu has collaborated with top research institutions, universities, and tech companies to further his research and bring his inventions to life. His collaborative efforts have led to the successful implementation of his innovative ideas.

Conclusion: In conclusion, Kuang-Wen Liu's passion for innovation and his dedication to pushing the boundaries of technology have solidified his reputation as a pioneering inventor in the field of semiconductor technology. His contributions continue to inspire future generations of inventors and shape the technological landscape for years to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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