Macronix International Co., Ltd.

Macronix Internationalco., Ltd.

Macronix International, Col, Ltd.

Kuang-Wen Liu

Chong-Jen Huang

Hsin-Huei Chen

Chih-Hao Wang

Ting-Feng Liao

Jia-Rong Chiou

Cheng-Wei Lin

Chih-Yuan Wu

Kuang-Chao Chen

Kai-Hsiang Chang

Yuan-Chieh Chiu

Jui-Lin Lu

Yao-An Chung

Ching-Chang Lin

Chong-Mu Chen

Zheng-Chang Mu

Chih-Lin Chen

Kuan-Chih Chen

Yi-Chen Wang

Jr-Meng Wang

Meng-Han Tsai

Mao-yuan Weng

Sheng-Hong Chen

A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Method for fabricating memory device

Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.

Memory devices with multiple string select line cuts

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a source line structure. The source line structure includes a composite material formed in a trench. The composite material includes an oxide portion and a metal portion.

3D memory device including source line structure comprising composite material

A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.

Memory device and method for fabricating the same

A semiconductor device includes a substrate, a stacked structure disposed on the substrate, and dummy memory string structures. The stacked structure includes alternately stacked insulating layers and conductive layers. The dummy memory string structures disposed in a staircase region of the semiconductor device penetrate the stacked structure along a first direction. The staircase region includes a body portion including a first region and a second region adjacent to the first region. In the first region, an amount of conductive layers corresponding to the dummy memory string structures is between 1 and 10; in the second region, an amount of conductive layers corresponding to the dummy memory string structures is greater than 10. An area of the dummy memory string structures in the first region is greater than an area of the dummy memory string structures in the second area under an identical unit area in a top view.

Semiconductor device and method for fabricating the same

The semiconductor structure includes a semiconductor device, a first metallization layer on the semiconductor device, a second metallization layer on the first metallization layer, and a third dielectric layer between the first metallization layer and the second metallization layer. The first metallization layer includes a first dielectric layer and a first metal layer disposed in the first dielectric layer, wherein the first metal layer has a first thickness, and the first metal layer comprises copper. The third dielectric layer has a second thickness, and a ratio of the second thickness of the third dielectric layer to the first thickness of the first metal layer is ranged from about 3 to about 20.

Semiconductor structure and method of fabricating wiring structure

Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

Photo pattern method to increase via etching rate

Provided is a method for fabricating a memory device including forming a stack layer on a substrate, and embedding a plurality of gate pillar structures and a plurality of dielectric pillars in the stack layer. The plurality of gate pillar structures and the plurality of dielectric pillars extend along a same direction and are alternately arranged, so that the stack layer is divided into a plurality of stack structures.

Provided is a memory device, including a plurality of gate pillar structures and a plurality of dielectric pillars. The gate pillar structures and the dielectric pillars are arranged alternately and separately along a first direction, and are arranged alternately and contact each other along a second direction. In addition, the gate pillar structures and the dielectric pillars are embedded in a stack layer along a third direction, thereby dividing the stack layer into a plurality of stack structures. A sidewall of each of the dielectric pillars in the second direction and a sidewall of the adjacent gate pillar structure in the second direction are not coplanar.

An improved semiconductor device is provided whereby the semiconductor device is defined by a layered structure comprising a first dielectric layer, a data storage material disposed on the first dielectric layer, and a second dielectric layer disposed on the data storage material, the layered structured substantially forming the outer layer of the semiconductor device. For example, the semiconductor device may be a SONOS structure having an oxide-nitride-oxide (ONO) film that substantially surrounds the SONOS structure. The invention also provides methods for fabricating the semiconductor device and the SONOS structure of the invention.

Sonos device and method for fabricating the same

A memory device is provided, which includes a plurality of gate pillar structures and a plurality of dielectric pillars extending alternately arranged along a same direction and embedding in a stack layer so that the stack layer divided into a plurality of stack structures.

A line layout method includes: forming i core layers each including a main layer that extends in a first direction and has a first end and a second end, and an end layer that is connected with the first end of the main layer and protrudes in a second direction; forming a first spacer on a sidewall of the core layer; removing the core layers; and forming 2i auxiliary patterns. i is an integer equal to or greater than 1. The auxiliary patterns extend in the first direction and are spaced and arranged in the first direction. In a region corresponding to the end layer, a portion not overlapping the auxiliary patterns has an I-beam shape.

Line layout and method of spacer self-aligned quadruple patterning for the same

An improved semiconductor device is provided whereby the semiconductor device is defined by a layered structure comprising a first dielectric layer, a data storage material disposed on the first dielectric layer, and a second dielectric layer disposed on the data storage material, the layered structured substantially forming the outer later of the semiconductor device. For example, the semiconductor device may be a SONOS structure having an oxide-nitride-oxide (ONO) film that substantially surrounds the SONOS structure. The invention also provides methods for fabricating the semiconductor device and the SONOS structure of the invention.

SONOS device and method for fabricating the same

A method of fabricating memory devices is provided. First, a charge storage structure including a gate dielectric structure is formed on the substrate in sequence to form a charge trapping layer. Then, a gate conductive layer is formed above the charge storage structure. Afterwards, the gate conductive layer and at least a part of the charge storage structure are patterned. The cross section of the patterned charge storage structure is then become a trapezoid or a trapezoid analogue, which has the shorter side near the gate conductive layer and the longer side near the substrate.

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Hsinchu, Taiwan

Kuang-Wen Liu