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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11917828 B1

PDFFull Text
Date of Patent:
Feb. 27, 2024

Filed:

May. 07, 2021

Memory devices with multiple string select line cuts

Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Ting-Feng Liao, Hsin-chu, TW;

Mao-Yuan Weng, Hualien, TW;

Kuang-Wen Liu, Hsin-chu, TW;

Assignee:

Macronix International Co., Ltd., Hsinchu, TW;

Attorney:

Fish & Richardson P.C.

Primary Examiner:

Reema Patel

Int. Cl.
CPC ...
H10B 41/00 (2023.01); H10B 43/50 (2023.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/50 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/50 (2023.02); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/50 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.

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