Kanagawa, Japan

Kiyoshi Kato

This inventor holds 460 USPTO granted patents and 37 published patent applications and 13 EPO patents, primarily in Semiconductor Devices (CPC class H01L27-1225). Top assignee: Semiconductor Energy Laboratory Co., Ltd.. Active years: 2003-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kiyoshi Kato. Retrieved from https://idiyas.com/inventor/kiyoshi-kato

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 460 

% Patents Active = 49.3

 

Average Co-Inventor Count = 2.3

ph-index = 31

Forward Citations = 4,437(Granted Patents)

Forward Citations (Not Self Cited) = 3,547(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Kanagawa-Ken, JP (2009)
  • Isehara, JP (2010 - 2015)
  • Sagamihara, JP (2005 - 2018)
  • Kanagawa, JP (2003 - 2024)
  • Atsugi, JP (2005 - 2024)

Company Filing History:


Years Active: 2003-2026

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Areas of Expertise:
Semiconductor Device
Memory Device
Display Apparatus
High Frequency Amplifier
Dynamic Logic Circuit
Error Detection
Stacked Element Layers
Imaging Device
Three Transistor
Electronic Component
460 patents (USPTO):Explore Patents

Title: Kiyoshi Kato: Innovator and Semiconductor Expert

Introduction:

Kiyoshi Kato is a renowned innovator and semiconductor expert based in Kanagawa, Japan. With an impressive track record boasting 428 patents, Kato has made significant contributions to the field of semiconductor devices. This article explores his latest patents, career highlights, and collaborations within the industry.

Latest Patents:

Among Kato's recent inventions is a semiconductor device designed to maintain connection relations between logic circuit units, even when the power supply voltage is interrupted. This device also allows for high-speed changes in the connection relations and circuit configurations of each logic circuit unit. Kato achieved this by utilizing the potential of oxide semiconductors in the channel formation region of the semiconductor element.

Additionally, Kato has developed a semiconductor device with a memory region that can be modified at different levels. The memory device in this invention consists of a first and a second memory circuit, along with a control circuit. By adjusting the voltage applied to the back gate of certain transistors in the memory circuits, Kato enables the modification of each memory region.

Career Highlights:

Kiyoshi Kato's groundbreaking work in the semiconductor field has established him as an industry leader. Throughout his career, he has made significant advancements in the development of semiconductor devices, with a particular focus on oxide semiconductors. His contributions in maintaining connection relations between logic circuit units, reconfigurable circuits, and flexible memory regions have had a profound impact on the industry.

Collaborations:

Kato has had the privilege of working alongside esteemed colleagues in the industry as he continues pushing the boundaries of semiconductor technology. Notable collaborations include his partnerships with Shunpei Yamazaki and Jun Koyama. These collaborations have allowed Kato to combine his expertise with the unique perspectives and skills of his colleagues, resulting in innovative solutions and patent-worthy inventions.

Conclusion:

Kiyoshi Kato's relentless pursuit of innovation in the semiconductor field has yielded an impressive portfolio of 428 patents. His expertise in oxide semiconductors and their applications in logic circuit units, reconfigurable circuits, and memory regions has solidified his position among the top innovators in the industry. With his commitment to pushing technological boundaries and collaborating with industry peers, Kato's contributions continue to shape the semiconductor landscape.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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