Semiconductor Energy Laboratory Co., Ltd.

Kiyoshi Kato

Shunpei Yamazaki

Jun Koyama

Yutaka Shionoiri

Takanori Matsuzaki

Shuhei Nagatsuka

Tatsuya Onuki

Tomoaki Atsumi

Hiroki Inoue

Toshihiko Saito

Masahiko Hayakawa

Atsuo Isobe

Takahiko Ishizu

Mitsuaki Osame

Satoshi Murakami

Yuto Yakubo

Hajime Kimura

Hidetomo Kobayashi

Hidekazu Miyairi

Tamae Takano

Munehiro Azami

Wataru Uesugi

Yusuke Sekine

Tadafumi Ozaki

Kohei Mutaguchi

Hiroyuki Miyake

Yoshiyuki Kurokawa

Yuta Endo

Satoru Okamoto

Masashi Fujita

Saishi Fujikawa

Kazuma Furutani

Takayuki Ikeda

Koichiro Kamata

Konami Izumi

Tatsuji Nishijima

Yoshinori Ieda

Toru Takayama

Yasuyuki Arai

Masayuki Sakakura

Junya Maruyama

Ryoji Nomura

Yuugo Goto

Yumiko Ohno

Hitoshi Kunitake

Shuhei Maeda

Takehisa Sato

Yasuhiko Takemura

Nobuharu Ohsawa

Hisashi Ohtani

Hideomi Suzawa

Hiromichi Godo

Atsushi Miyaguchi

Takuro Ohmaru

Hajime Tokunaga

Yoshitaka Moriya

Eiji Sugiyama

Yasuyuki Takahashi

Junpei Sugao

Tatsunori Inoue

Makoto Yanagisawa

Yuki Hata

Etsuko Asano

Asami Tadokoro

Nozomi Horikoshi

Hideaki Kuwabara

Yoshiaki Oikawa

Tetsuji Yamaguchi

Takeshi Osada

Tetsuhiro Tanaka

Yoshitaka Yamamoto

Hiroko Abe

Yoshinobu Asami

Masataka Nakada

Yasumasa Yamane

Masakazu Murakami

Mikio Yukawa

Toshihiko Takeuchi

Hironobu Shoji

Takayuki Inoue

Tsutomu Murakawa

Ryota Imahayashi

Seiya Saito

Satoshi Seo

Akihisa Shimomura

Daisuke Matsubayashi

Mai Akiba

Yuki Okamoto

Seiichi Yoneda

Keitaro Imai

Katsuaki Tochibayashi

Atsushi Hirose

Yuichi Yanagisawa

Shinpei Matsuda

Ryo Tokumaru

Kazuaki Ohshima

Takahiro Tsuji

Haruyuki Baba

Satohiro Okamoto

Kazuki Tsuda

An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

Semiconductor device

A semiconductor device having a novel structure is provided. The semiconductor device includes a first element layer including a first memory cell, a second element layer including a second memory cell, and a silicon substrate including a driver circuit. The first element layer is provided between the silicon substrate and the second element layer. The first memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. One of a source and a drain of the first transistor and one of a source and a drain of the second transistor are each electrically connected to a wiring for electrical connection to the driver circuit. The wiring is in contact with a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor and is provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate.

Semiconductor device and electronic device having stacked element layers on driver-circuit substrate

A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.

A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, abnormality in shape, or dielectric breakdown is inhibited is provided. The semiconductor device includes a first region and a second region over the same plane. The first region includes a transistor. The second region includes a dummy transistor. The transistor includes a first wiring layer, a semiconductor layer including an oxide and provided above the first wiring layer, a second wiring layer provided above the semiconductor layer, and a third wiring layer provided above the second wiring layer. The dummy transistor has the same area as one or more selected from the first wiring layer, the second wiring layer, the semiconductor layer, and the third wiring layer.

An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.

Semiconductor device and dynamic logic circuit

A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Memory device and electronic device

A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.

Semiconductor device, memory device, and electronic device

A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

Memory device having error detection function, semiconductor device, and electronic device

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

A semiconductor device is provided in which power consumption is reduced and an increase in circuit area is inhibited. The semiconductor device includes a high frequency amplifier circuit, an envelope detection circuit, and a power supply circuit. The power supply circuit has a function of supplying a power supply potential to the high frequency amplifier circuit, an output of the high frequency amplifier circuit is connected to the envelope detection circuit, and an output of the envelope detection circuit is connected to the power supply circuit. The power supply circuit can reduce the power consumption by changing the power supply potential in accordance with the output of the high frequency amplifier circuit. The use of an OS transistor in the envelope detection circuit can inhibit an increase in circuit area.

Semiconductor device including high frequency amplifier circuit, electronic component, and electronic device

An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

Imaging device and electronic device

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Kanagawa, Japan

Kiyoshi Kato