The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Apr. 18, 2023
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Tatsuya Onuki, Kanagawa, JP;

Takanori Matsuzaki, Kanagawa, JP;

Kiyoshi Kato, Kanagawa, JP;

Shunpei Yamazaki, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 11/4091 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 5/02 (2013.01); G11C 5/063 (2013.01); H10B 12/30 (2023.02);
Abstract

A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.


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