Tomoaki Atsumi

Kanagawa, Japan

Tomoaki Atsumi

This inventor holds 112 USPTO granted patents and 30 published patent applications and 6 EPO patents, primarily in Semiconductor Devices (CPC class H01L29-7869). Top assignee: Semiconductor Energy Laboratory Co., Ltd.. Active years: 2004-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tomoaki Atsumi. Retrieved from https://idiyas.com/inventor/tomoaki-atsumi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 112 

% Patents Active = 50.0

 

Average Co-Inventor Count = 2.9

ph-index = 16

Forward Citations = 847(Granted Patents)

Forward Citations (Not Self Cited) = 771(Dec 10, 2025)


Inventors with similar research interests:

🔬 See more inventors

Location History:

  • Atsugi, JP (2005 - 2010)
  • Isehara, JP (2007 - 2014)
  • Kanagawa, JP (2004 - 2024)
  • Hadano, JP (2015 - 2024)

Company Filing History:


Years Active: 2004-2025

Loading Chart...
Loading Chart...
Areas of Expertise:
Semiconductor Device
Memory Device
Display Apparatus
Dynamic Logic Circuit
Error Detection
Electronic Component
Microcontroller
Wireless Sensor
Central Control System
Manufacturing Method
Peripheral Circuit
Transistor
112 patents (USPTO):Explore Patents

Title: Innovations by Tomoaki Atsumi in Semiconductor Technology

Introduction

Tomoaki Atsumi, based in Kanagawa, Japan, is an esteemed inventor recognized for his significant contributions to the field of semiconductor technology. With an impressive portfolio of 109 patents, he has played a critical role in advancing innovations that enhance the performance and efficiency of semiconductor devices. His work primarily focuses on developing devices that support greater data storage capabilities and faster operating speeds.

Latest Patents

Among his latest inventions are two notable patents centered on semiconductor devices and memory technologies. The first patent describes a semiconductor device and dynamic logic circuit designed to increase operating speeds. This device features a memory cell comprising three transistors of a single conductivity type and a capacitor, all intelligently connected to various lines and wires to optimize performance.

The second patent outlines a memory device that incorporates an error detection function while maximizing data storage per unit area. This innovation uses a driver circuit formed on a semiconductor substrate alongside memory cells utilizing thin-film transistors. This design not only supports error detection but also allows for stacking multiple layers of memory cells, thereby increasing the storage capacity of the device significantly.

Career Highlights

Tomoaki Atsumi's career is distinguished by his persistent pursuit of innovation in the semiconductor industry. He currently works at Semiconductor Energy Laboratory Co., Ltd., where he collaborates with a team of talented professionals dedicated to advancing semiconductor technology. His extensive work and commitment to innovation have earned him recognition among peers and industry leaders alike.

Collaborations

Throughout his career, Tomoaki has collaborated with notable colleagues, including Kiyoshi Kato and Yutaka Shionoiri. These collaborations have fostered a creative environment that has led to the development of groundbreaking technologies that expand the possibilities within the semiconductor field.

Conclusion

Tomoaki Atsumi stands as a pivotal figure in semiconductor innovation, exemplified by his impressive number of patents and significant contributions to high-performance devices. His ongoing work at Semiconductor Energy Laboratory Co., Ltd. and his collaborations with other esteemed professionals illustrate his commitment to pushing the boundaries of technology, ultimately benefiting industries reliant on advanced semiconductor solutions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…