The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Jul. 24, 2023
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Tomoaki Atsumi, Kanagawa, JP;

Shuhei Nagatsuka, Kanagawa, JP;

Tamae Moriwaka, Kanagawa, JP;

Yuta Endo, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 69/00 (2023.01); G11C 7/16 (2006.01); G11C 8/14 (2006.01); G11C 11/24 (2006.01); G11C 11/403 (2006.01); G11C 11/408 (2006.01); H01L 27/06 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H10B 41/20 (2023.01); H10B 41/70 (2023.01);
U.S. Cl.
CPC ...
H10B 69/00 (2023.02); G11C 7/16 (2013.01); G11C 8/14 (2013.01); G11C 11/24 (2013.01); G11C 11/403 (2013.01); G11C 11/4085 (2013.01); H01L 27/0688 (2013.01); H01L 29/24 (2013.01); H01L 29/7869 (2013.01); H10B 41/20 (2023.02); H10B 41/70 (2023.02);
Abstract

[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.


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