Semiconductor Energy Laboratory Co., Ltd.

Tomoaki Atsumi

Kiyoshi Kato

Yutaka Shionoiri

Shunpei Yamazaki

Shuhei Nagatsuka

Jun Koyama

Hidetomo Kobayashi

Masayuki Sakakura

Tatsuya Onuki

Atsuo Isobe

Takanori Matsuzaki

Yuta Endo

Takayuki Ikeda

Satoshi Murakami

Masato Ishii

Tamae Moriwaka

Yosuke Tsukamoto

Yoshiyuki Kurokawa

Takeshi Osada

Hiroki Inoue

Tatsuji Nishijima

Hitoshi Kunitake

Kazuaki Ohshima

Kazunori Watanabe

Junpei Sugao

Yoshinori Ieda

Masafumi Ito

Hiroyuki Miyake

Koji Kusunoki

Takashi Okuda

Susumu Kawashima

Munehiro Azami

Takahiko Ishizu

Yuto Yakubo

Shuhei Maeda

Satoshi Yoshimoto

Ryunosuke Honda

Yoshiya Takewaki

Hajime Kimura

Masaaki Hiroki

Yoshiyuki Kobayashi

Tetsuhiro Tanaka

Hikaru Tamura

Seiichi Yoneda

Yoshitaka Yamamoto

Takuro Ohmaru

Konami Izumi

Yutaka Okazaki

Shinpei Matsuda

Wataru Uesugi

Yasuyuki Takahashi

Hiroki Dembo

Haruyuki Baba

Naoaki Tsutsui

Suguru Hondo

Kazuki Tanemura

Yoko Tsukamoto

A novel correction method of a display apparatus is provided. One embodiment of the present invention is a correction method of a display apparatus. The correction method includes processing in which a voltage correcting a threshold voltage of the transistor is obtained and the voltage is held in the capacitor; processing in which current flowing through the pixel is measured and a second signal based on the current is generated in the first circuit; processing in which the first signal correcting image data using the second signal is generated in the second circuit; and processing in which the first signal is supplied to the pixel.

Correction method of display apparatus including pixel and plurality of circuits

A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, abnormality in shape, or dielectric breakdown is inhibited is provided. The semiconductor device includes a first region and a second region over the same plane. The first region includes a transistor. The second region includes a dummy transistor. The transistor includes a first wiring layer, a semiconductor layer including an oxide and provided above the first wiring layer, a second wiring layer provided above the semiconductor layer, and a third wiring layer provided above the second wiring layer. The dummy transistor has the same area as one or more selected from the first wiring layer, the second wiring layer, the semiconductor layer, and the third wiring layer.

Semiconductor device

A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.

Semiconductor device and dynamic logic circuit

A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

Memory device having error detection function, semiconductor device, and electronic device

Provided is a highly reliable semiconductor device. The present invention relates to a shift register circuit including a plurality of stages of sequential circuits. An output signal of a sequential circuit is input to a sequential circuit in the subsequent stage. Before a sequential circuit outputs a signal and after the sequential circuit outputs the signal, the potential of a gate of a transistor included in the sequential circuit is changed in accordance with a clock signal so as to avoid voltage stress application between the gate and a source of the transistor for a long time. The shift register circuit can be applied to a scan line driver circuit of a display apparatus, for example.

Semiconductor device, display apparatus, and electronic device

A novel semiconductor device formed with single-polarity circuits using OS transistors is provided. Thus, connection between different layers in a memory circuit is unnecessary. This can reduce the number of connection portions and improve the flexibility of circuit layout and the reliability of the OS transistors. In particular, many memory cells are provided; thus, the memory cells are formed with single-polarity circuits, whereby the number of connection portions can be significantly reduced. Further, by providing a driver circuit in the same layer as the cell array, many wirings for connecting the driver circuit and the cell array can be prevented from being provided between layers, and the number of connection portions can be further reduced. An interposer provided with a plurality of integrated circuits can function as one electronic component.

Semiconductor device, electronic component, and electronic device

[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

A semiconductor device having a light sensing function and including a high-resolution display portion is provided. The semiconductor device includes a plurality of pixels, and the pixels each include first and second light-receiving devices, first to fifth transistors, a capacitor, and a first wiring. One electrode of the first light-receiving device is electrically connected to the first wiring, and the other electrode is electrically connected to one of a source and a drain of the first transistor. One electrode of the second light-receiving device is electrically connected to the first wiring, and the other electrode is electrically connected to one of a source and a drain of the second transistor. The other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor, one of a source and a drain of the third transistor, and a gate of the fourth transistor.

Semiconductor device and electronic device

The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.

Semiconductor device and method for driving semiconductor device

A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.

Memory device

A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.

A semiconductor device capable of obtaining the threshold voltage of a transistor is provided. The semiconductor device includes a first transistor, a first capacitor, a first output terminal, a first switch, and a second switch. A gate and a source of the first transistor are electrically connected to each other. A first terminal of the first capacitor is electrically connected to the source. A second terminal and the first output terminal of the first capacitor are electrically connected to a back gate of the first transistor. The first switch controls input of a first voltage to the back gate. A second voltage is input to a drain of the first transistor. The second switch controls input of a third voltage to the source.

Semiconductor device and operation method thereof

To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j&#x2265;2, the jth sub memory cell is arranged over the j-lth sub memory cell.

A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.

A semiconductor device that writes data to, instead of a defective memory cell, another memory cell is provided. The semiconductor device includes a first circuit and a second circuit over the first circuit; the first circuit corresponds to a memory portion and includes a memory cell and a redundant memory cell; a second circuit corresponds to a control portion and includes a third circuit and a fourth circuit. The memory cell is electrically connected to the third circuit, the redundant memory cell is electrically connected to the third circuit, and the third circuit is electrically connected to the fourth circuit. The fourth circuit has a function of sending data to be written to the memory cell or the redundant memory cell to the third circuit, and the third circuit has a function of bringing the memory cell and the fourth circuit into a non-conduction state and the redundant memory cell and the fourth circuit into a conduction state to send the data to the redundant memory cell when the memory cell is a defective cell.

Semiconductor device comprising memory cells

Growing community of inventors

Kanagawa, Japan

Tomoaki Atsumi