The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2025
Filed:
Feb. 21, 2019
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Shunpei Yamazaki, Tokyo, JP;
Kiyoshi Kato, Kanagawa, JP;
Tomoaki Atsumi, Kanagawa, JP;
Shuhei Nagatsuka, Kanagawa, JP;
Hitoshi Kunitake, Kanagawa, JP;
Yoko Tsukamoto, Kanagawa, JP;
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Abstract
A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, abnormality in shape, or dielectric breakdown is inhibited is provided. The semiconductor device includes a first region and a second region over the same plane. The first region includes a transistor. The second region includes a dummy transistor. The transistor includes a first wiring layer, a semiconductor layer including an oxide and provided above the first wiring layer, a second wiring layer provided above the semiconductor layer, and a third wiring layer provided above the second wiring layer. The dummy transistor has the same area as one or more selected from the first wiring layer, the second wiring layer, the semiconductor layer, and the third wiring layer.