The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2025
Filed:
Nov. 19, 2019
Semiconductor device and electronic device having stacked element layers on driver-circuit substrate
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Tatsuya Onuki, Atsugi, JP;
Yuto Yakubo, Atsugi, JP;
Yuki Okamoto, Isehara, JP;
Seiya Saito, Atsugi, JP;
Kiyoshi Kato, Atsugi, JP;
Shunpei Yamazaki, Setagaya, JP;
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Abstract
A semiconductor device having a novel structure is provided. The semiconductor device includes a first element layer including a first memory cell, a second element layer including a second memory cell, and a silicon substrate including a driver circuit. The first element layer is provided between the silicon substrate and the second element layer. The first memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. One of a source and a drain of the first transistor and one of a source and a drain of the second transistor are each electrically connected to a wiring for electrical connection to the driver circuit. The wiring is in contact with a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor and is provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate.