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For the Inventor, By the Inventor

Kuala Lumpur, Malaysia

Jun Pin Tan

This inventor holds 22 USPTO granted patents and 4 published patent applications and 5 EPO patents, primarily in Integrated Circuit Design. Top assignees: Altera Corporation, Intel Corporation. Active years: 2009-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jun Pin Tan. Retrieved from https://idiyas.com/inventor/jun-pin-tan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 22 

% Patents Active = 86.4

 

Average Co-Inventor Count = 3.0

ph-index = 5

Forward Citations = 63(Granted Patents)


Location History:

  • Kuala Lampur, MY (2009)
  • Selangor, MY (2014 - 2019)
  • Kepong, MY (2013 - 2022)
  • Kuala Lumpur, MY (2010 - 2024)

Company Filing History:

goldMedal13 out of 4,335 
 
Altera Corporation
 patents
silverMedal9 out of 56,394 
 
Intel Corporation
 patents

Years Active: 2009-2024

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Areas of Expertise:
Integrated Circuit
Programmable Logic Device
Memory Caching
Error Detection
Data Encoding
FPGA Configuration
Hardware Emulation
Interconnect Routing
Dynamic Characterization
Configuration Bit Stream
Non-Destructive Readback
Performance Optimization
22 patents (USPTO):Explore Patents
1. 12086460 - Non-destructive readback and writeback for integrated circuit device (2024-09-10),
2. 11487445 - Programmable integrated circuit with stacked memory die for storing configuration data (2022-11-01),
3. 11334263 - Configuration or data caching for programmable logic device (2022-05-17),
4. 11257526 - Sector-aligned memory accessible to programmable logic fabric of programmable logic device (2022-02-22),
5. 11223361 - Interface for parallel configuration of programmable devices (2022-01-11),
6. 11086788 - Methods and apparatus for accessing configurable memory during hardware emulation (2021-08-10),
7. 10666265 - Interface for parallel configuration of programmable devices (2020-05-26),
8. 10528413 - Criticality-based error detection (2020-01-07),
9. 10243561 - Interleaving scheme for increasing operating efficiency during high current events on an integrated circuit (2019-03-26),
10. 10186305 - High speed FPGA boot-up through concurrent multi-frame configuration scheme (2019-01-22),
11. 9627019 - High speed FPGA boot-up through concurrent multi-frame configuration scheme (2017-04-18),
12. 9401190 - High speed FPGA boot-up through concurrent multi-frame configuration scheme (2016-07-26),
13. 9383802 - Integrated circuit with state and data retention (2016-07-05),
14. 8941408 - Configuring data registers to program a programmable device with a configuration bit stream without phantom bits (2015-01-27),
15. 8629689 - Integrated circuit with improved interconnect routing and associated methods (2014-01-14),

Title: Inventor Jun Pin Tan - Revolutionizing Technology in Kuala Lumpur

Introduction: Jun Pin Tan is a visionary inventor based in Kuala Lumpur, Malaysia, known for his groundbreaking contributions to the field of technology.

Latest Patents: Jun Pin Tan holds several patents in the areas of artificial intelligence, renewable energy, and sustainable technologies, showcasing his commitment to innovation and sustainability.

Career Highlights: With a career spanning over two decades, Jun Pin Tan has worked with leading tech companies in Malaysia, spearheading research and development projects that have led to significant technological advancements.

Collaborations: Throughout his career, Jun Pin Tan has collaborated with top researchers, engineers, and scientists both locally and internationally, fostering a culture of innovation and knowledge sharing.

Conclusion: Jun Pin Tan's relentless pursuit of innovation and his passion for creating a sustainable future through technology make him a prominent figure in the inventor community in Kuala Lumpur and beyond.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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