Altera Corporation

Intel Corporation

Jun Pin Tan

Kiun Kiet Jong

Scott J Weber

Aravind Raghavendra Dasu

Boon Jin Ang

Ravi Prakash Gutala

Kar Keng Chua

Lai Pheng Tan

Sean R Atsatt

James Loran Ball

Bee Yee Ng

Kevin Clark

Simon S Chong

Chuan Khye Chai

Tze Swan Tan

Arifur Rahman

Jayabrata Ghosh Dastidar

Wei Yee Koay

David J Greenhill

Choong Kit Wong

Yi Peng

Guang Chen

Archanna Srinivasan

Yee Liang Tan

Tat Mun Lui

Siew Ling Yeoh

Chiew Khiang Kuit

Kok Sun Chia

Guang Sheng Soh

Systems and methods for non-destructive readback and writeback of an integrated circuit system are provided. Such a system may include an adaptive logic element including a first register pair. The first register pair may include a first register operating at a first frequency and a second register operating at a second frequency. The second frequency may be equal to or lower than the first frequency. The second register may store data from the first register. The adaptive logic element may also include a first clock providing a first clock signal to the first register and a second clock providing a second clock signal. The adaptive logic element may also include a multiplexer that may select the first clock signal or the second clock signal as a clock source for the second register.

Non-destructive readback and writeback for integrated circuit device

A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.

Programmable integrated circuit with stacked memory die for storing configuration data

An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include programmable logic fabric having configuration memory and programmable logic elements controlled by the configuration memory, and sector-aligned memory apart from the programmable logic fabric. A first sector of the configuration memory may be programmed with first configuration data. The sector-aligned memory may include a first sector of sector-aligned memory that may cache the first configuration data while the configuration memory is programmed with the first configuration data a first time. A second sector of sector-aligned memory may cache second configuration data for a second sector of the configuration memory in parallel while the first sector of sector-aligned memory caches the first configuration data for the first sector of the configuration memory.

Configuration or data caching for programmable logic device

An integrated circuit device may include programmable logic fabric on a first integrated circuit die and sector-aligned memory on a second integrated circuit die to enable large amounts of data to be rapidly processed by a sector of programmable logic of the programmable logic device. The programmable logic fabric may include a first and second sectors. The first sector may be programmed with a circuit design that operates on a first set of data. The sector-aligned memory may include a first sector of sector-aligned memory directly accessible by the first sector of programmable logic fabric and a second sector of sector-aligned memory directly accessible by the second sector of programmable logic fabric. The first sector of sector-aligned memory may store the first set of data.

Sector-aligned memory accessible to programmable logic fabric of programmable logic device

An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

Interface for parallel configuration of programmable devices

Programmable integrated circuits may be used to perform hardware emulation of an application-specific integrated circuit (ASIC) design. The ASIC design may be loaded onto the programmable integrated circuit as a device under test (DUT). During hardware emulation operations, an emulation host may be used to coordinate testing of the DUT on the programmable device. In particular, the programmable device may include configurable memory elements such as lookup-table random-access memory (LUTRAM) elements that are operable in a LUT mode and a memory mode. An emulation controller may be used to dynamically assert a global emulation request signal, which forces each LUTRAM element that belong to the DUT in the LUT mode, thereby allowing the emulation host to readily access their internal states without having to perform partial reconfiguration.

Methods and apparatus for accessing configurable memory during hardware emulation

A prioritized error detection schedule may be generated using computer-aided-design (CAD) tools that receive specifications of critical regions within an array of configuration random access memory (CRAM) cells on an integrated circuit. Each of the specified critical regions may be provided a respective criticality weight. The proportion of indices in a prioritized error detection schedule that prescribe error detection for a given critical region may be based on the criticality weight of the given critical region. A prioritized error detection schedule may prescribe more frequent error correction for critical regions with higher criticality weights relative to critical regions with lower criticality weights. Addressing circuitry on the integrated circuit may be used to read out data from critical regions of CRAM in the order prescribed by the prioritized error detection schedule and check the read out CRAM data for errors.

Criticality-based error detection

An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.

Interleaving scheme for increasing operating efficiency during high current events on an integrated circuit

Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

High speed FPGA boot-up through concurrent multi-frame configuration scheme

A method of operating an integrated circuit that includes a plurality of registers may include receiving a sleep mode request for the integrated circuit. The sleep mode request may be a control signal received with control circuitry on the integrated circuit. The plurality of registers may be configured to operate as a scan chain when the sleep mode request is received. Integrated circuit state information that are stored in the plurality of registers may be retrieved by operating the scan chain and stored in a memory module. The integrated circuit may be placed in a sleep mode. Placing the integrated circuit in the sleep mode may reduce power consumption of the integrated circuit.

Integrated circuit with state and data retention

Techniques and mechanisms dynamically configure shift registers among registers composing data registers in a circuit such as a Programmable Logic Device (PLD). A configuration bit stream used to configure the PLD may have a reduced size if 'phantom bits' not corresponding to configuration elements are removed. Shift registers may be dynamically configured such that registers which do not correspond to physical configuration elements may be skipped. Thus, a PLD may be programmed with a configuration bit stream without phantom bits.

Configuring data registers to program a programmable device with a configuration bit stream without phantom bits

An integrated circuit (IC) includes a circuit, an encoder, and a decoder. The circuit is coupled to circuitry in the IC via a first set of interconnect fabricated using a metal layer. The encoder encodes a plurality of address lines to provide a plurality of encoded address lines. The decoder decodes the plurality of address lines. The plurality of encoded address lines are routed using a second set of interconnect fabricated using the metal layer.

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Kuala Lumpur, Malaysia

Jun Pin Tan