The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

May. 18, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Jun Pin Tan, Kepong, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/1009 (2016.01); G11C 29/00 (2006.01); G11C 29/04 (2006.01); G06F 30/33 (2020.01); G06F 30/331 (2020.01); G11C 29/08 (2006.01); G11C 29/48 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G11C 29/00 (2013.01); G11C 29/08 (2013.01); G11C 29/48 (2013.01); G06F 30/33 (2020.01); G06F 30/331 (2020.01); G11C 2029/0401 (2013.01);
Abstract

Programmable integrated circuits may be used to perform hardware emulation of an application-specific integrated circuit (ASIC) design. The ASIC design may be loaded onto the programmable integrated circuit as a device under test (DUT). During hardware emulation operations, an emulation host may be used to coordinate testing of the DUT on the programmable device. In particular, the programmable device may include configurable memory elements such as lookup-table random-access memory (LUTRAM) elements that are operable in a LUT mode and a memory mode. An emulation controller may be used to dynamically assert a global emulation request signal, which forces each LUTRAM element that belong to the DUT in the LUT mode, thereby allowing the emulation host to readily access their internal states without having to perform partial reconfiguration.


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