The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Jun. 29, 2016
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Jun Pin Tan, Selangor, MY;

Kiun Kiet Jong, Penang, MY;

Lai Pheng Tan, Penang, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); H03K 19/177 (2006.01); G11C 8/04 (2006.01); G11C 7/00 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 8/04 (2013.01); G11C 7/00 (2013.01); H03K 19/1776 (2013.01); H03K 19/17776 (2013.01); G11C 7/1039 (2013.01);
Abstract

Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).


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