The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Jan. 11, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Scott J. Weber, Piedmont, CA (US);

David Greenhill, Portola Valley, CA (US);

Sean R. Atsatt, Santa Cruz, CA (US);

Ravi Prakash Gutala, San Jose, CA (US);

Aravind Raghavendra Dasu, Milpitas, CA (US);

Jun Pin Tan, Kuala Lumpur, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0802 (2016.01); G06F 12/0873 (2016.01); H03K 19/17736 (2020.01); G11C 7/22 (2006.01); G11C 5/02 (2006.01); G06F 12/0875 (2016.01); G06F 30/34 (2020.01); G11C 5/04 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0632 (2013.01); G06F 3/0613 (2013.01); G06F 3/0673 (2013.01); G06F 12/0802 (2013.01); G06F 12/0873 (2013.01); G06F 12/0875 (2013.01); G06F 30/34 (2020.01); G11C 5/025 (2013.01); G11C 7/22 (2013.01); H03K 19/17744 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/284 (2013.01); G06F 2212/45 (2013.01); G06F 2212/452 (2013.01); G11C 5/04 (2013.01); G11C 7/1039 (2013.01); G11C 2207/2245 (2013.01);
Abstract

An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include programmable logic fabric having configuration memory and programmable logic elements controlled by the configuration memory, and sector-aligned memory apart from the programmable logic fabric. A first sector of the configuration memory may be programmed with first configuration data. The sector-aligned memory may include a first sector of sector-aligned memory that may cache the first configuration data while the configuration memory is programmed with the first configuration data a first time. A second sector of sector-aligned memory may cache second configuration data for a second sector of the configuration memory in parallel while the first sector of sector-aligned memory caches the first configuration data for the first sector of the configuration memory.


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