The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Sep. 28, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kevin Clark, San Jose, CA (US);

Scott J. Weber, San Jose, CA (US);

James Ball, San Jose, CA (US);

Simon Chong, San Jose, CA (US);

Ravi Prakash Gutala, San Jose, CA (US);

Aravind Raghavendra Dasu, San Jose, CA (US);

Jun Pin Tan, Kuala Lumpur, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); G06F 7/38 (2006.01); H03K 19/1776 (2020.01); H03K 19/17768 (2020.01); H03K 19/17704 (2020.01); H03K 19/17758 (2020.01);
U.S. Cl.
CPC ...
H03K 19/1776 (2013.01); H03K 19/17708 (2013.01); H03K 19/17758 (2020.01); H03K 19/17768 (2013.01);
Abstract

An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.


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