IDiyas

For the Inventor, By the Inventor

Chandler, AZ, United States of America

Javier Soto Gonzalez

USPTO Granted Patents = 37 

 

Average Co-Inventor Count = 4.4

ph-index = 7

Forward Citations = 191(Granted Patents)


Company Filing History:

goldMedal36 out of 54,664 
 
Intel Corporation
 patents
silverMedal1 out of 82 
 
Tahoe Research, Ltd.
 patents

Years Active: 2011-2025

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37 patents (USPTO):
1. 12218071 - Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers (2025-02-04),
2. 12199067 - Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same (2025-01-14),
3. 12068172 - Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB packages (2024-08-20),
4. 12002745 - High performance integrated RF passives using dual lithography process (2024-06-04),
5. 11881457 - Semiconductor packaging with high density interconnects (2024-01-23),
6. 11735531 - Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers (2023-08-22),
7. 11532584 - Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling (2022-12-20),
8. 11227825 - High performance integrated RF passives using dual lithography process (2022-01-18),
9. 11107766 - Substrate with embedded stacked through-silicon via die (2021-08-31),
10. 11101222 - Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers (2021-08-24),
11. 11004824 - Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same (2021-05-11),
12. 10978399 - Die interconnect substrate, an electrical device, and a method for forming a die interconnect substrate (2021-04-13),
13. 10971453 - Semiconductor packaging with high density interconnects (2021-04-06),
14. 10971416 - Package power delivery using plane and shaped vias (2021-04-06),
15. 10872872 - Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling (2020-12-22),

Title: The Innovative Journey of Inventor Javier Soto Gonzalez

Introduction:

Meet Javier Soto Gonzalez, a prolific inventor hailing from Chandler, AZ, US, with an impressive portfolio of 33 patents to his name. His groundbreaking work in semiconductor packaging and panel level packaging has revolutionized the industry.

Latest Patents:

Among his latest patents is the "Semiconductor packaging with high density interconnects," where he introduced a semiconductor package with a unique design featuring conducting layers, dielectric layers, and interconnect regions. Another notable patent is "Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers," showcasing his expertise in forming conductive vias for multi-die products.

Career Highlights:

Javier Soto Gonzalez has made significant contributions during his tenure at renowned companies such as Intel Corporation and Tahoe Research, Ltd. His innovative spirit and dedication to pushing the boundaries of technology have earned him well-deserved recognition in the industry.

Collaborations:

Throughout his career, Javier has collaborated with esteemed professionals like Aleksandar Aleksov and John Stephen Guzek. Their collective efforts have led to the development of cutting-edge solutions in the semiconductor packaging domain.

Conclusion:

In conclusion, Javier Soto Gonzalez stands out as a trailblazing inventor in the field of semiconductor packaging, with a proven track record of delivering groundbreaking patents. His relentless pursuit of innovation continues to inspire the next generation of inventors and shape the future of technology.

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