The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Sep. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Adel A. Elsherbini, Chandler, AZ (US);

Johanna M. Swan, Scottsdale, AZ (US);

Shawna M. Liff, Scottsdale, AZ (US);

Henning Braunisch, Phoenix, AZ (US);

Krishna Bharath, Chandler, AZ (US);

Javier Soto Gonzalez, Chandler, AZ (US);

Javier A. Falcon, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 25/065 (2006.01); H01L 25/03 (2006.01); H01L 23/498 (2006.01); H01L 25/18 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/00 (2013.01); H01L 24/17 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/03 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 25/18 (2013.01); H01L 2224/18 (2013.01); H01L 2224/214 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06582 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/15153 (2013.01);
Abstract

Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.


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