Intel Corporation

Tahoe Research, Ltd.

Javier Soto Gonzalez

Adel A Elsherbini

Aleksandar Aleksov

Srinivas V Pietambaram

John Stephen Guzek

Kristof Darmawikarta

Robert Alan May

Krishna Bharath

Feras Eid

Rahul N Manepalli

Sri Ranga Sai Boyapati

Ravi Kiran Nalla

Houssam Jomaa

Meizi Jiao

Shawna M Liff

Henning Braunisch

Mathew J Manusharow

Suddhasattwa Nad

Drew W Delaney

Johanna M Swan

Yonggang Li

Digvijay Ashokkumar Raorane

Dilan Seneviratne

Nicholas Randolph Watts

Hamid Azimi

Kwangmo Lim

Telesphor Kamgaing

Robert L Sankman

William J Lambert

Mihir K Roy

Wei-Lun Kane Jen

Brandon M Rawlings

Yidnekachew S Mekonnen

Javier A Falcon

Mohit Mamodia

Sashi S Kandanur

Kwangmo Chris Lim

Shruti Rajeev Jaywant

Rajat Goyal

Debendra Mallik

Sasha N Oster

Mauro J Kobrinsky

Islam A Salama

Kyu Oh Lee

Robert M Nickerson

Vivek Raghunathan

Tarek A Ibrahim

Robert Starkston

Edward Rudolph Prack

Braxton L Lathrop

Steve S Cho

Nadine L Dabby

Jason M Gamba

Oscar Ojeda

Edward A Zarbock

Srinivas Venkata Ramanuja Pietambaram

Tatyana N Andryushchenko

Charavana K Gurumurthy

Patrick Nardi

Roy Dittler

Sri Ranga Sai Sai Boyapati

David W Staines

Alejandro X Levander

Suresh V Pothukuchi

Keith D Jones

Zheng Zhou

David Q Xu

Lay Wai Kong

Rafiqul Islam

Ravi K Nailla

Hamid R Azimi

A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers

An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.

Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same

Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.

Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB packages

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

High performance integrated RF passives using dual lithography process

Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

Semiconductor packaging with high density interconnects

Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.

Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling

A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

Substrate with embedded stacked through-silicon via die

A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect, wherein the bridge die is embedded in the multilayer substrate structure. The die interconnect substrate comprises a via portion formed on the first bridge die pad of the bridge die. An average angle between a surface of the first bridge die pad and a sidewall of the via portion lies between 85&#xb0; and 95&#xb0;.

Die interconnect substrate, an electrical device, and a method for forming a die interconnect substrate

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

Package power delivery using plane and shaped vias

Growing community of inventors

Chandler, AZ, United States of America

Javier Soto Gonzalez