The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2021
Filed:
Jul. 30, 2019
Intel Corporation, Santa Clara, CA (US);
Krishna Bharath, Chandler, AZ (US);
Mathew J. Manusharow, Phoenix, AZ (US);
Adel A. Elsherbini, Chandler, AZ (US);
Mihir K. Roy, Chandler, AZ (US);
Aleksandar Aleksov, Chandler, AZ (US);
Yidnekachew S. Mekonnen, Chandler, AZ (US);
Javier Soto Gonzalez, Chandler, AZ (US);
Feras Eid, Chandler, AZ (US);
Suddhasattwa Nad, Chandler, AZ (US);
Meizi Jiao, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.