The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Jul. 30, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Tarek A. Ibrahim, Mesa, AZ (US);

Rahul N. Manepalli, Chandler, AZ (US);

Wei-Lun K. Jen, Chandler, AZ (US);

Steve S. Cho, Chandler, AZ (US);

Jason M. Gamba, Gilbert, AZ (US);

Javier Soto Gonzalez, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4846 (2013.01); H01L 21/481 (2013.01); H01L 23/49838 (2013.01); H01L 23/5386 (2013.01); H01L 23/5385 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19105 (2013.01);
Abstract

Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.


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