Chandler, AZ, United States of America

Wei-Lun Kane Jen

This inventor holds 35 USPTO granted patents and 12 published patent applications and 2 EPO patents, primarily in Semiconductor Packaging. Top assignee: Intel Corporation. Active years: 2016-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Wei-Lun Kane Jen. Retrieved from https://idiyas.com/inventor/wei-lun-kane-jen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 35 

% Patents Active = 94.3

 

Average Co-Inventor Count = 4.8

ph-index = 6

Forward Citations = 84(Granted Patents)


Company Filing History:


Years Active: 2016-2026

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Areas of Expertise:
Low-Permittivity Core
High Density Routing
Magnetic Core Inductors
Underfill Containment
Microelectronic Structures
Die Interconnect Substrate
Asymmetric Electronic Substrate
Silane Adhesion Promoter
Multilayer Substrate
Solder Resist Layers
Embedded Interconnect Bridge
High Resolution Solder Resist
35 patents (USPTO):Explore Patents

Title: Innovations by Wei-Lun Kane Jen in Electronic Packaging Technology

Introduction:

Wei-Lun Kane Jen, based in Chandler, AZ, is a prominent inventor in the field of electronic packaging technology. With a remarkable portfolio of 30 patents, his contributions have significantly advanced the efficiency and reliability of electronic devices.

Latest Patents:

His latest patents include "Sacrificial Pads to Prevent Galvanic Corrosion of FLI Bumps in EMIB Packages". This innovation outlines electronic packages and methods for their production, focusing on an array of first level interconnect (FLI) bumps designed to enhance performance by mitigating galvanic corrosion. The invention details the construction of a package substrate with a first pad and a second pad, facilitating electrical coupling for improved function.

Another recent patent is "Device and Method of Very High Density Routing Used with Embedded Multi-Die Interconnect Bridge." This invention presents a method to enhance bridge structures with conducting and insulating layers that are lithographically processed. The described structure incorporates ultra-Fine Line Scale (uFLS) routing to provide high-density connectivity between die, significantly optimizing performance in complex electronic systems.

Career Highlights:

Wei-Lun Kane Jen is currently employed at Intel Corporation, where he continues to push the boundaries of electronic packaging technology. His significant achievements in patent filings not only showcase his innovative mindset but also reflect his commitment to advancing the industry.

Collaborations:

Throughout his career, Wei-Lun has collaborated with notable colleagues, including Mihir K Roy and Amruthavalli Pallavi Alur. These partnerships have fostered an environment of innovation, allowing for the exchange of ideas and expertise, which is essential for groundbreaking developments in technology.

Conclusion:

Wei-Lun Kane Jen is a visionary inventor whose work at Intel Corporation has made substantial contributions to the field of electronic packaging. Through his innovative patents, he exemplifies the critical role of inventors in driving technological advancements that improve device functionality and reliability. As his career progresses, the electronics industry can anticipate further innovations from this talented individual.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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