The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Jul. 03, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sri Chaitra Jyotsna Chavali, Chandler, AZ (US);

Tarek Ibrahim, Mesa, AZ (US);

Wei-Lun Jen, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 49/02 (2006.01); H05K 1/18 (2006.01); H01L 23/48 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); H01L 21/76877 (2013.01); H01L 23/481 (2013.01); H01L 23/645 (2013.01); H01L 28/10 (2013.01); H05K 1/181 (2013.01); H05K 2201/1003 (2013.01);
Abstract

Embodiments herein describe techniques for a semiconductor device including a package substrate having a core layer. An inductor may include a first coaxial line and a second coaxial line vertically through the core layer, and an interconnect within the package substrate coupling the first coaxial line and the second coaxial line. A first magnetic segment may surround the first coaxial line within the core layer, and a second magnetic segment may surround the second coaxial line within the core layer. In addition, a third magnetic segment may surround the interconnect and be coupled to the first magnetic segment and the second magnetic segment. Other embodiments may be described and/or claimed.


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