The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Aug. 21, 2018
Applicant:

Intel Corporation, Chandler, AZ (US);

Inventors:

Krishna Bharath, Chandler, AZ (US);

Wei-Lun Jen, Chandler, AZ (US);

Huong Do, Chandler, AZ (US);

Amruthavalli Alur, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01F 17/00 (2006.01); H01F 27/26 (2006.01); H01L 23/00 (2006.01); H01L 23/64 (2006.01); H10D 1/20 (2025.01); H01F 17/04 (2006.01);
U.S. Cl.
CPC ...
H10D 1/20 (2025.01); H01F 17/0033 (2013.01); H01F 27/266 (2013.01); H01L 23/5226 (2013.01); H01L 23/5227 (2013.01); H01L 23/645 (2013.01); H01L 24/03 (2013.01); H01L 24/09 (2013.01); H01F 2017/0086 (2013.01);
Abstract

A microelectronics package comprises a substrate comprising at least two conductive layers that are separated by a first dielectric. At least one island comprising a magnetic material is embedded within the dielectric between the two conductive layers. An inductor structure extends within a via in the at least one island. The via extends between the two conductive layers. The inductor structure comprises a conductive wall along a sidewall of the via, and wherein the conductive wall surrounds a second dielectric and is electrically coupled to the two conductive layers.


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