The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Sep. 29, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Srinivas V. Pietambaram, Gilbert, AZ (US);

Sri Ranga Sai Boyapati, Chandler, AZ (US);

Robert A. May, Chandler, AZ (US);

Kristof Darmawikarta, Chandler, AZ (US);

Javier Soto Gonzalez, Chandler, AZ (US);

Kwangmo Lim, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 23/00 (2013.01); H01L 24/06 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/18 (2013.01); H01L 2224/24137 (2013.01); H01L 2924/18162 (2013.01);
Abstract

A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.


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