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For the Inventor, By the Inventor

Singapore, Singapore

James Yong Meng Lee

This inventor holds 27 USPTO granted patents and 1 published patent application and 1 EPO patent, primarily in CMOS Technology. Top assignees: Chartered Semiconductor Manufacturing Ltd (Corporation), Globalfoundries Singapore Pte. Ltd., Other. Active years: 2001-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: James Yong Meng Lee. Retrieved from https://idiyas.com/inventor/james-yong-meng-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 27 

% Patents Active = 59.3


Average Co-Inventor Count = 5.4

ph-index = 12

Forward Citations = 518(Granted Patents)


Company Filing History:

goldMedal23 out of 962 
 
Chartered Semiconductor Manufacturing Ltd (Corporation)
 patents
silverMedal3 out of 1,060 
 
Globalfoundries Singapore Pte. Ltd.
 patents
bronzeMedal1 out of 834,513 
Other
 patents

Years Active: 2001-2012

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Areas of Expertise:
Shallow Trench Isolation
Vertical Transistor
High-K Dielectrics
Self-Aligned CMOS
Gate Electrode Patterning
Ultra-Thin Gate Dielectric
Variable-K Gate Dielectric
Microtrench Formation
MOSFET Performance
Memory Cell Structure
Transistor Channel Control
Isolated Transistors
27 patents (USPTO):Explore Patents
1. 8178417 - Method of forming shallow trench isolation structures for integrated circuits (2012-05-15),
2. 8143651 - Nested and isolated transistors with reduced impedance difference (2012-03-27),
3. 7999300 - Memory cell structure and method for fabrication thereof (2011-08-16),
4. 7767577 - Nested and isolated transistors with reduced impedance difference (2010-08-03),
5. 7037791 - Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates (2006-05-02),
6. 6747314 - Method to form a self-aligned CMOS inverter using vertical device integration (2004-06-08),
7. 6709934 - Method for forming variable-K gate dielectric (2004-03-23),
8. 6541327 - Method to form self-aligned source/drain CMOS device on insulated staircase oxide (2003-04-01),
9. 6475916 - Method of patterning gate electrode with ultra-thin gate dielectric (2002-11-05),
10. 6468877 - Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner (2002-10-22),
11. 6461887 - Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth (2002-10-08),
12. 6458717 - Methods of forming ultra-thin buffer oxide layers for gate dielectrics (2002-10-01),
13. 6455377 - Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) (2002-09-24),
14. 6440800 - Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers (2002-08-27),
15. 6436774 - Method for forming variable-K gate dielectric (2002-08-20),

Title: James Yong Meng Lee: Innovator in Integrated Circuit Patents

Introduction

James Yong Meng Lee is a prominent inventor based in Singapore, known for his exceptional contributions in the field of integrated circuit technologies. With a remarkable portfolio of 27 patents, he has played a significant role in advancing innovation within the semiconductor industry.

Latest Patents

Among his latest patents, Lee has developed a method of forming shallow trench isolation structures for integrated circuits. This innovative technique utilizes a multi-step etch process, where the first etch selectively targets the substrate at a substantially higher etching rate than the mask layer, resulting in preliminary openings with steep taper angles. The subsequent etch step non-selectively deepens these openings, creating STI gaps with flat bottoms, which is essential for enhancing circuit performance.

Another notable patent outlines a process for creating nested and isolated transistors with reduced impedance difference. This is achieved by forming a processing layer, such as silicon, on a metal silicide contact, followed by a metal layer. By annealing the silicon and metal layers, the thickness of the metal silicide contact is increased selectively, allowing for improved matching of transistors in both iso and nested regions.

Career Highlights

James has had a successful career with significant contributions while working at reputable companies such as Chartered Semiconductor Manufacturing Ltd and Globalfoundries Singapore Pte. Ltd. These experiences have enriched his understanding and ability to innovate within the semiconductor domain, allowing him to create and patent cutting-edge technologies.

Collaborations

During his career, Lee has collaborated with distinguished professionals, including his coworkers Ravi Sundaresan and Lap Chan. Through these partnerships, he has been able to exchange ideas and drive forward innovative solutions in integrated circuit design and manufacturing.

Conclusion

James Yong Meng Lee stands out as a notable inventor in Singapore’s semiconductor industry. With his extensive patent portfolio and collaborations with industry experts, he continues to push the boundaries of innovation in integrated circuit technologies. His contributions not only enhance the performance of electronic devices but also pave the way for future advancements in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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