The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2002
Filed:
Jul. 13, 2000
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
Abstract
A first option is a method of forming an ultra thin buffer oxide layer comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided. The silicon substrate has an upper surface. A sacrificial oxide layer is formed over the silicon substrate and the STI regions. Oxygen is implanted within the silicon substrate. The oxygen implant having a peak concentration proximate the upper surface of the silicon substrate. The sacrificial oxide layer is stripped and removed. A gate dielectric layer is formed over the silicon substrate. A conductor layer is deposited over the gate dielectric layer. The structure is annealed to form ultra-thin buffer oxide layer between the silicon substrate and the gate dielectric layer. A second option is a method of forming an ultra-thin buffer oxide layer, comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided. The silicon substrate has an upper surface. A gate dielectric layer is formed over the silicon substrate and the STI regions. A sacrificial oxide layer is formed over the gate dielectric layer. Oxygen is implanted within the silicon substrate. The oxygen implant having a peak concentration proximate the upper surface of the silicon substrate. The sacrificial oxide layer is stripped and removed. A conductor layer is deposited over the gate dielectric layer. The structure is annealed to form ultra-thin buffer oxide layer between the silicon substrate and the gate dielectric layer.