The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2010
Filed:
Feb. 14, 2008
Johnny Widodo, Singapore, SG;
Liang Choo Hsia, Singapore, SG;
James Yong Meng Lee, Singapore, SG;
Wen Zhi Gao, Singapore, SG;
Zhao Lun, Singapore, SG;
Huang Liu, Singapore, SG;
Chung Woh Lai, Singapore, SG;
Shailendra Mishra, The Woodsvale, SG;
Yew Tuck Chow, Singapore, SG;
Fang Chen, Singapore, SG;
Shiang Yang Ong, Singapore, SG;
Johnny Widodo, Singapore, SG;
Liang Choo Hsia, Singapore, SG;
James Yong Meng Lee, Singapore, SG;
Wen Zhi Gao, Singapore, SG;
Zhao Lun, Singapore, SG;
Huang Liu, Singapore, SG;
Chung Woh Lai, Singapore, SG;
Shailendra Mishra, The Woodsvale, SG;
Yew Tuck Chow, Singapore, SG;
Fang Chen, Singapore, SG;
Shiang Yang Ong, Singapore, SG;
Chartered Semiconductor Manufacturing, Ltd., Singapore, SG;
Abstract
A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rof transistors in iso and nested regions can be matched.