Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Other

James Yong Meng Lee

Lap Chan

Ravi Sundaresan

Jia Zhen Zheng

Yang Pan

Ying Keung Leung

Elgin Kiok Quek

Yelehanka Ramachandramurthy Pradeep

Chung Woh Lai

Johnny Widodo

Zhao Lun

Shailendra Mishra

Huang Liu

Liang Choo Hsia

Wen Zhi Gao

Shiang Yang Ong

Fang Chen

Xia Li

Yew Tuck Chow

Yun Qiang Zhang

Shyue Seng Tan

Alex See

Elgin Kiok Boone Quek

Lee Wee Teo

Ganesh S Samudra

Chock Hing Gan

Jeffrey Chee

Lay Cheng Choo

Sneedharan Pillai Sneelal

C K Lau

Yelehanka Ramachandramurthy

Yunqzang Zhang

Francis Youg Wee Poh

A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.

Method of forming shallow trench isolation structures for integrated circuits

A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rof transistors in iso and nested regions can be matched.

Nested and isolated transistors with reduced impedance difference

A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.

Memory cell structure and method for fabrication thereof

In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.

Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates

A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.

Method to form a self-aligned CMOS inverter using vertical device integration

A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

Method for forming variable-K gate dielectric

A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.

Method to form self-aligned source/drain CMOS device on insulated staircase oxide

A new method is provided for the creation of ultra-thin gate oxide layers. Under the first embodiment, sacrificial oxide and nitride are deposited, openings are created in the layer of nitride where the ultra-thin layer of gate oxide is to be created. A layer of poly is deposited over the layer of nitride. The layer of polysilicon is polished, leaving the poly deposited inside the openings. The nitride is removed leaving the gate structure in place overlying the grown gate oxide. Under the second embodiment, sacrificial oxide and nitride are deposited followed by the deposition of TEOS oxide. The layers of TEOS, oxide and nitride are patterned creating openings that expose the surface areas of the layer of sacrificial oxide where the ultra-thin layers of gate oxide are to be grown. A thin conformal layer of nitride is deposited over the structure, this thin layer of conformal nitride is etched to form thin spacers on the sidewalls of the openings in the layers of TEOS oxide and nitride. Pre-gate clean is performed that removes the TEOS oxide and the sacrificial oxide on the bottom of the openings, gate oxidation is performed creating the ultra-thin layers of gate oxide. Poly is deposited, polished back followed by removal of the nitride leaving the poly gate structure in place and overlying the ultra-thin layer of gate oxide.

Method of patterning gate electrode with ultra-thin gate dielectric

A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.

Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner

A method of forming an inverted staircase shaped STI structure comprising the following steps. A semiconductor substrate having an overlying oxide layer is provided. The substrate having at least a pair of active areas defining an STI region therebetween. The oxide layer is etched a first time within the active areas to form first step trenches. The first step trenches having exposed sidewalls. Continuous side wall spacers are formed on said exposed first step trench sidewalls. The oxide layer is etched X&plus;1 more successive times using the previously formed step side wall spacers as masks to form successive step trenches within the active areas. Each of the successive step trenches having exposed sidewalls and have side wall spacers successively formed on the successive step trench exposed sidewalls. The oxide layer is etched a final time using the previously formed step side wall spacers as masks to form final step trenches exposing the substrate within the active areas. The STI region comprising an inverted staircase shaped STI structure. The step side wall spacers are removed from the X&plus;2 step trenches. A planarized active area silicon structure is formed within the X&plus;2 and final step trenches.

Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth

A first option is a method of forming an ultra thin buffer oxide layer comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided. The silicon substrate has an upper surface. A sacrificial oxide layer is formed over the silicon substrate and the STI regions. Oxygen is implanted within the silicon substrate. The oxygen implant having a peak concentration proximate the upper surface of the silicon substrate. The sacrificial oxide layer is stripped and removed. A gate dielectric layer is formed over the silicon substrate. A conductor layer is deposited over the gate dielectric layer. The structure is annealed to form ultra-thin buffer oxide layer between the silicon substrate and the gate dielectric layer. A second option is a method of forming an ultra-thin buffer oxide layer, comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided. The silicon substrate has an upper surface. A gate dielectric layer is formed over the silicon substrate and the STI regions. A sacrificial oxide layer is formed over the gate dielectric layer. Oxygen is implanted within the silicon substrate. The oxygen implant having a peak concentration proximate the upper surface of the silicon substrate. The sacrificial oxide layer is stripped and removed. A conductor layer is deposited over the gate dielectric layer. The structure is annealed to form ultra-thin buffer oxide layer between the silicon substrate and the gate dielectric layer.

Methods of forming ultra-thin buffer oxide layers for gate dielectrics

A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.

Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)

A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

Growing community of inventors

Singapore, Singapore

James Yong Meng Lee