Hsinchu, Taiwan

Hung-Hsin Hsu

This inventor holds 82 USPTO granted patents and 28 published patent applications, primarily in Semiconductor Packaging (CPC class H01L21-568). Top assignees: Powertech Technology Inc., Asia Ic Mic-Process, Inc.. Active years: 2009-2026.

USPTO Granted Patents = 82 

% Patents Active = 76.8

Average Co-Inventor Count = 2.5

ph-index = 6

Forward Citations = 174(Granted Patents)

Forward Citations (Not Self Cited) = 166(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Hsinchu, TW (2009 - 2017)
  • Qionglin Township, Hsinchu County, TW (2019)
  • Hukou Township, Hsinchu County, TW (2019 - 2023)
  • Hsinchu County, TW (2018 - 2024)
  • Taipei, TW (2019 - 2024)

Company Filing History:


Years Active: 2009-2026

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Areas of Expertise:
Semiconductor Package
Integrated Antenna
Chip Package
Manufacturing Method
Stacked Package
Redistribution Layer
Conductive Element
Molding Layer
Connection Circuit
Thermal Management
3D Stacking
Material Mixing
82 patents (USPTO):Explore Patents

Hung-Hsin Hsu, a talented inventor from Hsinchu County, Taiwan, has made significant contributions to the field of semiconductor packaging. With 73 patents to his name, he has demonstrated his expertise and creativity in this specialized area.

One of Hsu's recent patents is titled "Semiconductor package comprising a plurality of bumps and fabricating method." This invention involves a semiconductor package with multiple bumps and a novel fabrication method. The package includes a chip, first and second bumps, an encapsulation, and a redistribution layer. The chip comprises pads and an active area, with the first area housing the pads and the second area surrounding them. The first bump is formed on each corresponding pad, while the second bumps, which have different width layers, are formed on the second area. The encapsulation covers the chip and bumps and is ground to expose the bumps. Notably, the grinding process ensures that all first bumps are completely exposed, preventing any shallow-grinding or over-grinding issues and maintaining proper electrical connectivity.

Another inventive contribution by Hsu is his patent for a package structure that includes multiple dies surrounded by a conductive element. This package structure also features a dielectric body, a circuit layer, and a patterned insulating layer. The conductive element encompasses the multiple dies, and the dielectric body covers them. The circuit layer is electrically connected to the multiple dies, and the patterned insulating layer covers the circuit layer. This arrangement allows for optimized performance and functionality.

Hung-Hsin Hsu has collaborated with several prominent companies throughout his career. He has worked with Asia IC Mic-Process, Inc., which specializes in semiconductor manufacturing processes, and Powertech Technology Inc., a well-known provider of integrated circuit (IC) testing services.

During his collaborations, Hsu had the opportunity to work alongside talented individuals such as Nan-Chun Lin and Shang-Yu Chang Chien. Their combined expertise and dedication likely contributed to the success of their projects and inventions.

Hung-Hsin Hsu's patents and innovations in semiconductor packaging demonstrate his deep understanding of the field and his ability to develop practical solutions. His contributions have undoubtedly advanced the technology and manufacturing processes in the semiconductor industry.

Profile summary based on public USPTO records.
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